US6288585B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device using external power voltage for timing sensitive signals
Assignee: Socionext Inc
•
Filing: 2000-03-27
•
Granted: 2001-09-11
•
Expires: 2020-03-27
Abstract
Abstract A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.
Inventors
- 👤 Yoshihide Bando
- 👤 Nobutaka Taniguchi
- 👤 Hiroyoshi Tomita
- 👤 Kota Hara
- 👤 Naoharu Shinozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:12
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C7/00; G11C7/10; G11C7/1078; G11C7/1084; G11C7/1087; G11C7/22; G11C7/222; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
88 words
A semiconductor device receiving an external power voltage, comprising: a reduced-voltage-generation circuit which generates an internally reduced power voltage; an input circuit which operates based on the internally reduced power voltage; a clock-control circuit which generates an internal clock signal; an output circuit which outputs a data signal to an exterior of said device at output timings responsive to the internal clock signal; a clock-delivery circuit which conveys the internal clock signal from said clock-control circuit to said output circuit, and operates based on the external power voltage.
Claim 2
Dependent Claim
88 words
A semiconductor device receiving an external power voltage, comprising: a reduced-voltage-generation circuit which generates an internally reduced power voltage; an input circuit which operates based on the internally reduced power voltage; a clock-control circuit which generates an internal clock signal; an output circuit which outputs a data signal to an exterior of said device at output timings responsive to the internal clock signal; a clock-delivery circuit which conveys the internal clock signal from said clock-control circuit to said output circuit, and operates based on the external power voltage.
Claim 3
Dependent Claim
47 words
The semiconductor device as claimed in claim 1 , wherein said clock-delivery circuit includes a level-conversion circuit which converts signal levels of the internal clock signal from a signal level based on the internally reduced power voltage into a signal level based on the external power voltage.
Claim 4
Dependent Claim
17 words
The semiconductor device as claimed in claim 1 , wherein said clock-control circuit includes a DLL circuit.
Claim 5
Dependent Claim
37 words
The semiconductor device as claimed in claim 1 , further comprising another reduced-voltage-generation circuit which generates a dedicated power voltage by lowering the external power voltage, wherein said DLL circuit operates based on the dedicated power voltage.
Claim 6
Dependent Claim
126 words
A semiconductor device, comprising: a reduced-voltage-generation circuit which generates an internally reduced power voltage by reducing an external power voltage supplied from an exterior of said device; an input circuit which operates based on the internally reduced power voltage; a clock-control circuit which generates an internal clock signal; an output circuit which outputs a data signal to the exterior of said device at output timings responsive to the internal clock signal; a clock buffer circuit which buffers a clock signal supplied from the exterior of said device to supply the clock signal to said clock-control circuit, and operates based on the external power voltage; and buffer circuits which buffer signals supplied from the exterior of said device, and operate based on the internally reduced power voltage.
Claim 7
Dependent Claim
126 words
A semiconductor device, comprising: a reduced-voltage-generation circuit which generates an internally reduced power voltage by reducing an external power voltage supplied from an exterior of said device; an input circuit which operates based on the internally reduced power voltage; a clock-control circuit which generates an internal clock signal; an output circuit which outputs a data signal to the exterior of said device at output timings responsive to the internal clock signal; a clock buffer circuit which buffers a clock signal supplied from the exterior of said device to supply the clock signal to said clock-control circuit, and operates based on the external power voltage; and buffer circuits which buffer signals supplied from the exterior of said device, and operate based on the internally reduced power voltage.
Claim 8
Dependent Claim
45 words
The semiconductor device as claimed in claim 5 , wherein each of said buffer circuits includes an amplifier portion and a driver portion, said driver portion operating based on the internally reduced power voltage while said amplifier portion operates based on the external power voltage.
Claim 9
Dependent Claim
85 words
A semiconductor device, comprising: a reduced-voltage-generation circuit which generates an internally reduced power voltage by reducing an external power voltage supplied from an exterior of said device; an input circuit which operates based on the internally reduced power voltage; first buffer circuits which buffer first signals supplied from the exterior of said device, and operate based on the external power voltage; and second buffer circuits which buffer second signals supplied from the exterior of said device, and operate based on the internally reduced power voltage.
Claim 10
Dependent Claim
85 words
A semiconductor device, comprising: a reduced-voltage-generation circuit which generates an internally reduced power voltage by reducing an external power voltage supplied from an exterior of said device; an input circuit which operates based on the internally reduced power voltage; first buffer circuits which buffer first signals supplied from the exterior of said device, and operate based on the external power voltage; and second buffer circuits which buffer second signals supplied from the exterior of said device, and operate based on the internally reduced power voltage.
Claim 11
Dependent Claim
46 words
The semiconductor device as claimed in claim 7 , wherein each of said second buffer circuits includes an amplifier portion and a driver portion, said driver portion operating based on the internally reduced power voltage while said amplifier portion operates based on the external power voltage.
Claim 12
Dependent Claim
61 words
The semiconductor device as claimed in claim 7 , further comprising: a strobe-buffer circuit which buffers a strobe signal supplied from the exterior of said device; first latch circuits which receive the respective first signals from said first buffer circuits, and latch the respective first signals at rising edges and falling edges of the strobe signal supplied from said strobe-buffer circuit.
Claim 13
Dependent Claim
58 words
The semiconductor device as claimed in claim 9 , further comprising: a clock-buffer circuit which buffers a clock signal supplied from the exterior of said device; second latch circuits which receive the respective second signals from said second buffer circuits, and latch the respective second signals at rising edges of the clock signal supplied from said clock-buffer circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-10 | 2005-03-12 | 2005-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-10 | 2009-03-12 | 2009-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-10 | 2013-03-12 | 2013-09-11 | $7700.00 | Window Closed / Lapsed |