US6284571B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Lead frame assemblies with voltage reference plane and IC packages including same
Assignee: Micron Technology Inc
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Filing: 1999-05-25
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Granted: 2001-09-04
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Expires: 2019-05-25
Abstract
Abstract A semiconductor die assembly employing a voltage reference plane structure electrically isolated from, but in immediate proximity to, leads of a lead frame to which the die is electrically connected. A non-conductive adhesive or an adhesively-coated dielectric film is used to position the voltage reference plane on the leads. The voltage reference plane is electrically connected to a ground or other reference potential pin of the die through a connection to one of the leads. The assembly is encapsulated, preferably by transfer-molding of a filled polymer. More than one discrete voltage reference plane structure may be employed, for example, when the package is of an LOC configuration with two rows of leads, each having a voltage reference plane secured thereto, or a single voltage reference plane including major portions adhered to leads and interposed connection portions may be applied to all of the leads of an assembly.
Inventors
- 👤 David J. Corisis
- 👤 Jerry M. Brooks
- 👤 Terry R. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:09
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W70/421; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W72/851; H10W72/853; H10W72/865; H10W74/00; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
99 words
A method of reducing inductance associated with lead fingers of a lead frame electrically connected to bond pads of a semiconductor die, comprising: configuring a voltage reference plane to include a plurality of integral projections extending transversely therefrom on one side thereof; and positioning said voltage reference plane in superimposed, immediate proximity to at least one group of said lead fingers over at least a majority of a surface area of said at least one lead finger group and in electrical isolation therefrom with said plurality of integral projections extending away from said at least one lead finger group.
Claim 2
Independent Claim
99 words
A method of reducing inductance associated with lead fingers of a lead frame electrically connected to bond pads of a semiconductor die, comprising: configuring a voltage reference plane to include a plurality of integral projections extending transversely therefrom on one side thereof; and positioning said voltage reference plane in superimposed, immediate proximity to at least one group of said lead fingers over at least a majority of a surface area of said at least one lead finger group and in electrical isolation therefrom with said plurality of integral projections extending away from said at least one lead finger group.
Claim 3
Dependent Claim
27 words
The method of claim 1 , further comprising adhering said voltage reference plane to at least some of the lead fingers of said at least one group.
Claim 4
Dependent Claim
18 words
The method of claim 2 , wherein said adhering is effected by direct adherence through a non-conductive adhesive.
Claim 5
Dependent Claim
44 words
The method of claim 2 , wherein said adhering is effected by adhering said voltage reference plane to one surface of an insulating film and adhering at least some of said lead fingers of said group to an opposing surface of said insulating film.
Claim 6
Dependent Claim
21 words
The method of claim 1 , further comprising effecting an electrical connection to a lead finger of said lead finger group.
Claim 7
Dependent Claim
23 words
The method of claim 5 , further comprising connecting said lead finger through a bond pad to a ground of said semiconductor die.
Claim 8
Independent Claim
109 words
A method of fabricating a semiconductor device assembly, comprising: providing a lead frame strip having a plurality of substantially identical lead finger groups, each group associated with a die-attach location; configuring a plurality of voltage reference plane structures to include a plurality of integral projections extending transversely therefrom on one side thereof; and adhering at least one of said plurality of voltage reference plane structures by a side thereof opposing said one side in superimposition to at least a portion of some of the lead fingers of each lead finger group and over at least a majority of surface area of each lead finger group through an insulating structure.
Claim 9
Independent Claim
109 words
A method of fabricating a semiconductor device assembly, comprising: providing a lead frame strip having a plurality of substantially identical lead finger groups, each group associated with a die-attach location; configuring a plurality of voltage reference plane structures to include a plurality of integral projections extending transversely therefrom on one side thereof; and adhering at least one of said plurality of voltage reference plane structures by a side thereof opposing said one side in superimposition to at least a portion of some of the lead fingers of each lead finger group and over at least a majority of surface area of each lead finger group through an insulating structure.
Claim 10
Dependent Claim
48 words
The method of claim 7 , further comprising securing a semiconductor die to said lead frame strip at each of said respective die-attach locations, and electrically connecting each secured semiconductor die to at least some of the lead fingers of the group associated with the respective die-attach locations.
Claim 11
Dependent Claim
38 words
The method of claim 8 , wherein said securing is effected by attaching each said semiconductor die either directly to lead fingers of its associated group or to a die-attach paddle included with its associated lead finger group.
Claim 12
Dependent Claim
24 words
The method of claim 8 , further comprising electrically connecting a lead finger of each lead finger group to said voltage reference plane structures.
Claim 13
Dependent Claim
35 words
The method of claim 10 , further comprising encapsulating at least a portion of each said semiconductor die and a portion of its associated lead fingers with superimposed ground plane structure with a packaging material.
Claim 14
Dependent Claim
15 words
The method of claim 11 , wherein said encapsulating further comprises transfer-molding a filled polymer.
Claim 15
Dependent Claim
29 words
The method of claim 12 , further comprising severing each group of lead fingers with secured semiconductor die and adhered voltage reference plane structure from said lead frame strip.
Claim 16
Dependent Claim
28 words
The method of claim 7 , further comprising encapsulating at least a portion of said voltage reference plane structures and said lead frame strip with a packaging material.
Claim 17
Dependent Claim
15 words
The method of claim 14 , wherein said encapsulating comprises encapsulating said plurality of projections.
Claim 18
Independent Claim
90 words
A method of reducing inductance associated with a semiconductor device assembly, comprising: providing a leads over chip lead frame having lead fingers electrically connected to bond pads of a semiconductor die; positioning a voltage reference plane in immediate proximity to at least one group of said lead fingers and in electrical isolation therefrom so that said voltage reference plane is overlying at least a portion of said semiconductor die; and dielectrically adhesively affixing said at least one group of said lead fingers to an active surface of said semiconductor die.
Claim 19
Independent Claim
90 words
A method of reducing inductance associated with a semiconductor device assembly, comprising: providing a leads over chip lead frame having lead fingers electrically connected to bond pads of a semiconductor die; positioning a voltage reference plane in immediate proximity to at least one group of said lead fingers and in electrical isolation therefrom so that said voltage reference plane is overlying at least a portion of said semiconductor die; and dielectrically adhesively affixing said at least one group of said lead fingers to an active surface of said semiconductor die.
Claim 20
Dependent Claim
27 words
The method of claim 16 , further comprising adhering said voltage reference plane to at least some of the lead fingers of said at least one group.
Claim 21
Dependent Claim
18 words
The method of claim 17 , wherein said adhering is effected by direct adherence through a non-conductive adhesive.
Claim 22
Dependent Claim
44 words
The method of claim 17 , wherein said adhering is effected by adhering said voltage reference plane to one surface of an insulating film and adhering at least some of said lead fingers of said group to an opposing surface of said insulating film.
Claim 23
Dependent Claim
29 words
The method of claim 16 , further comprising effecting at least one electrical connection between the semiconductor die and at least one lead finger of said lead finger group.
Claim 24
Dependent Claim
31 words
The method of claim 20 , further comprising electrically connecting said at least one lead finger to said semiconductor die through a bond pad to a ground of said semiconductor die.
Claim 25
Independent Claim
125 words
A method of reducing inductance associated with lead fingers of a lead frame in a vertical surface mount package configuration electrically connected to bond pads of a semiconductor die, comprising: configuring and locating at least a first group of lead fingers and a second group of lead fingers of the lead frame to respectively extend from first and second opposing sides of an intended die-attach location to another, single side of the lead frame in a substantially mutually parallel configuration; positioning a first voltage reference plane to overlie in immediate proximity said first group of lead fingers and in electrical isolation therefrom; and positioning a second voltage reference plane to overlie in immediate proximity said second group of lead fingers and in electrical isolation therefrom.
Claim 26
Independent Claim
125 words
A method of reducing inductance associated with lead fingers of a lead frame in a vertical surface mount package configuration electrically connected to bond pads of a semiconductor die, comprising: configuring and locating at least a first group of lead fingers and a second group of lead fingers of the lead frame to respectively extend from first and second opposing sides of an intended die-attach location to another, single side of the lead frame in a substantially mutually parallel configuration; positioning a first voltage reference plane to overlie in immediate proximity said first group of lead fingers and in electrical isolation therefrom; and positioning a second voltage reference plane to overlie in immediate proximity said second group of lead fingers and in electrical isolation therefrom.
Claim 27
Dependent Claim
43 words
The method of claim 22 , further comprising adhering said first voltage reference plane and said second voltage reference plane to at least some of the lead fingers of said first group of lead fingers and said second group of lead fingers, respectively.
Claim 28
Dependent Claim
18 words
The method of claim 23 , wherein said adhering is effected by direct adherence through a non-conductive adhesive.
Claim 29
Dependent Claim
55 words
The method of claim 23 , wherein said adhering is effected by adhering said first voltage reference plane and said second voltage reference plane to one surface of an insulating film and adhering at least some of said lead fingers of said first and second group respectively to an opposing surface of said insulating film.
Claim 30
Dependent Claim
24 words
The method of claim 22 , further comprising effecting at least one electrical connection between the semiconductor die and at least one lead finger.
Claim 31
Dependent Claim
31 words
The method of claim 26 , further comprising electrically connecting said at least one lead finger to said semiconductor die through a bond pad to a ground of said semiconductor die.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-03 | 2005-03-05 | 2005-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-03 | 2009-03-05 | 2009-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-03 | 2013-03-05 | 2013-09-04 | $7700.00 | Window Closed / Lapsed |