Method and apparatus for performing power management by suppressing the speculative execution of instructions within a pipelined microprocessor

Claim 3

The method of claim 1 , wherein the suppression of the speculative execution of the instruction stream includes disabling the branch prediction circuitry.

Claim 4

Power management circuitry for reducing power consumption within a processor having a branch prediction capability, the power management circuitry comprising: a detector to detect a branch instruction within an instruction stream, the branch instruction being associated with either audio or video data; and a suppressor, coupled to the detector, to suppress speculative execution of the instruction stream within the processor responsive to the detection of the branch instruction associated with either audio or video data.

Claim 5

Power management circuitry for reducing power consumption within a processor having a branch prediction capability, the power management circuitry comprising: a detector to detect a branch instruction within an instruction stream, the branch instruction being associated with either audio or video data; and a suppressor, coupled to the detector, to suppress speculative execution of the instruction stream within the processor responsive to the detection of the branch instruction associated with either audio or video data.

Claim 6

The power management circuitry of claim 3 , wherein the suppressor is to disable the branch prediction circuitry.

Claim 7

A processor comprising: a branch prediction unit to output a prediction for a branch instruction and to steer an instruction stream in accordance with the output prediction; and a power management unit to detect the receipt at the processor of a branch instruction within an instruction stream, the branch instruction being associated with either audio or video data, and to suppress execution of the instruction stream prior to resolution of a branch condition, presented by a branch instruction within the instruction stream by the microprocessor responsive to the detection of the the branch instruction on account of the branch instruction being associated with the audio or video data.

Claim 8

A processor comprising: a branch prediction unit to output a prediction for a branch instruction and to steer an instruction stream in accordance with the output prediction; and a power management unit to detect the receipt at the processor of a branch instruction within an instruction stream, the branch instruction being associated with either audio or video data, and to suppress execution of the instruction stream prior to resolution of a branch condition, presented by a branch instruction within the instruction stream by the microprocessor responsive to the detection of the the branch instruction on account of the branch instruction being associated with the audio or video data.

Claim 9

The microprocessor of claim 5 wherein the power management unit is to disable the branch prediction unit so as to suppress speculative execution of the instruction.