Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
165 words
An electronic shutter camera with full frame resolution, said camera comprising: a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information; timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD; sync generator means for generating video timing signals; control means for resetting said timing means and said sync generator means, said control means including means for selecting an internal reset mode and an external reset mode of operation for said timing means and said sync generator means, said control means further including means responsive to an externally supplied asynchronous reset signal for resetting said timing means and said sync generator means; digital image generating means coupled to said CCD for generating multiple bit digital image signals; individual memory means coupled to said digital image generating means for storing a full frame multi-bit digital image; and means for converting said full frame multi-bit digital image to video signals having a selected format.
Claim 2
Dependent Claim
165 words
An electronic shutter camera with full frame resolution, said camera comprising: a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information; timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD; sync generator means for generating video timing signals; control means for resetting said timing means and said sync generator means, said control means including means for selecting an internal reset mode and an external reset mode of operation for said timing means and said sync generator means, said control means further including means responsive to an externally supplied asynchronous reset signal for resetting said timing means and said sync generator means; digital image generating means coupled to said CCD for generating multiple bit digital image signals; individual memory means coupled to said digital image generating means for storing a full frame multi-bit digital image; and means for converting said full frame multi-bit digital image to video signals having a selected format.
Claim 3
Dependent Claim
14 words
The invention of claim 1 wherein said CCD has a vertical overflow drain structure.
Claim 4
Dependent Claim
18 words
The invention of claim 1 wherein said control means includes manually selectable means for specifying the shutter speed.
Claim 5
Dependent Claim
40 words
The invention of claim 1 wherein said control means includes means responsive to a pair of externally supplied pulses for selecting the shutter speed in accordance with the time separation between preselected portions of said pair of externally supplied pulses.
Claim 6
Dependent Claim
23 words
The invention of claim 1 wherein said converting means includes means for outputting said frame image as interlaced successive fields of video information.
Claim 7
Dependent Claim
23 words
The invention of claim 1 wherein said converting means includes means for outputting said frame image as a non-interlaced frame of video information.
Claim 8
Dependent Claim
51 words
The invention of claim 1 wherein said individual memory means comprises a digital storage device having a memory capacity of at least one frame of information, and an analog to digital converter coupled between said CCD and said digital storage device for converting CCD analog output signals to digital equivalent signals.
Claim 9
Dependent Claim
37 words
The invention of claim 7 wherein said converting means includes a digital to analog converter coupled to said digital storage device for converting digital equivalent signals stored in said digital storage device to analog video output signals.
Claim 10
Dependent Claim
47 words
The invention of claim 7 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in a pixel sequential alternate line sequential order so that said analog video output signals are output in interlaced format as odd and even fields.
Claim 11
Dependent Claim
40 words
The invention of claim 7 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in pixel sequential line sequential order so that said analog video output signals are output in non-interlaced format.
Claim 12
Dependent Claim
134 words
An electronic shutter camera with full-frame resolution, said camera comprising: a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information; timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD; sync generator means for generating video timing signals; control means for resetting said timing means and said sync generator means; digital image generating means coupled to said CCD for generating multiple bit digital image signals; individual memory means coupled to said digital image generating means for storing a full-frame multi-bit digital image; and means for converting a full-frame multi-bit digital image to video signals having a selected format, said timing means, said sync generator means, said control means, said memory means and said converting means all being located within the camera.
Claim 13
Dependent Claim
134 words
An electronic shutter camera with full-frame resolution, said camera comprising: a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information; timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD; sync generator means for generating video timing signals; control means for resetting said timing means and said sync generator means; digital image generating means coupled to said CCD for generating multiple bit digital image signals; individual memory means coupled to said digital image generating means for storing a full-frame multi-bit digital image; and means for converting a full-frame multi-bit digital image to video signals having a selected format, said timing means, said sync generator means, said control means, said memory means and said converting means all being located within the camera.
Claim 14
Dependent Claim
127 words
An electronic shutter camera with full-frame resolution, said camera comprising: a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information; timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD; sync generator means for generating video timing signals; control means for resetting said timing means and said sync generator means in response to the receipt of an externally supplied asynchronous reset signal, said control means including means responsive to a pair of externally supplied pulses for selecting the shutter speed in accordance with the time separation between pre-selected portions of said pair of externally supplied pulses; and means for converting individual lines of said frame of information to video signals having a selected format.
Claim 15
Dependent Claim
127 words
An electronic shutter camera with full-frame resolution, said camera comprising: a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information; timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD; sync generator means for generating video timing signals; control means for resetting said timing means and said sync generator means in response to the receipt of an externally supplied asynchronous reset signal, said control means including means responsive to a pair of externally supplied pulses for selecting the shutter speed in accordance with the time separation between pre-selected portions of said pair of externally supplied pulses; and means for converting individual lines of said frame of information to video signals having a selected format.
Claim 16
Dependent Claim
26 words
The invention of claim 12 wherein said converting means includes means for outputting said individual lines of said frame of information to an interlaced video format.
Claim 17
Dependent Claim
26 words
The invention of claim 12 wherein said converting means includes means for outputting said individual lines of said frame of information to a non-interlaced video format.
Claim 18
Dependent Claim
45 words
The invention of claim 12 further including digital image generating means coupled to said CCD for generating multiple bit digital image signals; and wherein said converting means includes individual memory means coupled to said digital image generating means for storing a full-frame multi-bit digital image.
Claim 19
Dependent Claim
57 words
The invention of claim 15 wherein said memory means comprises a digital storage device having a memory capacity of at least one frame of information, and wherein said digital image generating means includes an analog to digital converter coupled between said CCD and said digital storage device for converting CCD analog output signals to digital equivalent signals.
Claim 20
Dependent Claim
38 words
The invention of the claim 16 wherein said converting means includes a digital to analog converter coupled to said digital storage device for converting digital equivalent signals stored in said digital storage device to analog video output signals.
Claim 21
Dependent Claim
47 words
The invention of claim 16 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in a pixel sequential alternative line sequential order so that said analog video output signals are output in interlaced format as odd and even fields.
Claim 22
Dependent Claim
40 words
The invention of claim 16 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in pixel sequential line sequential order so that said analog video output signals are output in non-interlaced format.