US6255689B1
Expired / Lapsed
US
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Flash memory structure and method of manufacture
Assignee: United Microelectronics Corp
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Filing: 1999-12-20
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Granted: 2001-07-03
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Expires: 2019-12-20
Abstract
Abstract A flash memory cell structure and its method of manufacture. The flash memory cell has a vertical configuration. An opening and then a trench are formed in a substrate by etching. The trench (defined as the recessed section of the substrate) is used for forming a shallow trench isolation structure. The substrate region between two neighboring openings (defined as the protruding section of the substrate) is used for forming a common drain and a channel. A source terminal is formed in the substrate at the upper comer next to the shallow trench structure. A tunnel oxide layer is formed over the substrate surface of the opening. A floating gate and a dielectric layer are formed over the tunnel oxide layer. A control gate is formed inside the opening.
Inventors
- 👤 Robin Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 18:10
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/684; H10D30/685; H10D30/6891; H10D30/6893
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
276 words
A method of manufacturing a flash memory, comprising the steps of: providing a substrate having a patterned mask layer thereon; transferring a pattern of the patterned mask layer to the substrate so that an opening is formed in the substrate; forming a first liner oxide layer over an exposed substrate inside the opening; forming spacers on sidewalls of the opening, wherein the each spacer has a first base width; forming a trench in the substrate at a bottom of the opening while using the patterned mask layer and the spacers as a hard mask; forming an insulation layer in the trench to form a shallow trench isolation structure; reducing the first base width of the spacers to a second base width; removing the patterned mask layer; forming a first doped region in the substrate next to an upper corner of the insulation layer and a second doped region in the substrate under the patterned mask layer, wherein the first doped region serves as a source terminal and the second doped region serves as a drain terminal; removing the spacers; forming an etching stop layer over the second doped region; forming a tunnel oxide layer over the substrate between the first and the second doped region; forming conductive spacers over the tunnel oxide coated sidewalls between the first and the second doped region; forming a first dielectric layer over the conductive spacers; forming a conductive layer inside the opening above the first dielectric layer; and patterning the conductive layer, the first dielectric layer and the conductive spacers to form a plurality of control gates, a plurality of second dielectric layers and a plurality of floating gates, respectively.
Claim 2
Independent Claim
276 words
A method of manufacturing a flash memory, comprising the steps of: providing a substrate having a patterned mask layer thereon; transferring a pattern of the patterned mask layer to the substrate so that an opening is formed in the substrate; forming a first liner oxide layer over an exposed substrate inside the opening; forming spacers on sidewalls of the opening, wherein the each spacer has a first base width; forming a trench in the substrate at a bottom of the opening while using the patterned mask layer and the spacers as a hard mask; forming an insulation layer in the trench to form a shallow trench isolation structure; reducing the first base width of the spacers to a second base width; removing the patterned mask layer; forming a first doped region in the substrate next to an upper corner of the insulation layer and a second doped region in the substrate under the patterned mask layer, wherein the first doped region serves as a source terminal and the second doped region serves as a drain terminal; removing the spacers; forming an etching stop layer over the second doped region; forming a tunnel oxide layer over the substrate between the first and the second doped region; forming conductive spacers over the tunnel oxide coated sidewalls between the first and the second doped region; forming a first dielectric layer over the conductive spacers; forming a conductive layer inside the opening above the first dielectric layer; and patterning the conductive layer, the first dielectric layer and the conductive spacers to form a plurality of control gates, a plurality of second dielectric layers and a plurality of floating gates, respectively.
Claim 3
Dependent Claim
17 words
The method of claim 1 , wherein the step of forming the spacers includes depositing silicon nitride.
Claim 4
Dependent Claim
54 words
The method of claim 1 , wherein after the step of forming the first and the second doped region, further includes forming a third doped region in the substrate under the second doped region next to the first doped region and a fourth doped region in the substrate under the shallow trench isolation structure.
Claim 5
Dependent Claim
35 words
The method of claim 3 , wherein ions used for forming the first and the second doped region have a polarity opposite to the ions used for forming the third and the fourth doped region.
Claim 6
Dependent Claim
54 words
The method of claim 1 , wherein before the step of forming the first and the second doped region, further includes forming a third doped region in the substrate under the second doped region next to the first doped region and a fourth doped region in the substrate under the shallow trench isolation structure.
Claim 7
Dependent Claim
37 words
The method of claim 5 , wherein ions used for forming the first and the second ped region have a polarity opposite to that of the ions used for forming the third and the fourth doped region.
Claim 8
Dependent Claim
18 words
The method of claim 1 , wherein the step of forming the conductive spacers includes depositing doped polysilicon.
Claim 9
Dependent Claim
18 words
The method of claim 1 , wherein the step of forming the conductive layer includes depositing doped polysilicon.
Claim 10
Dependent Claim
19 words
The method of claim 1 , wherein the step of forming the first dielectric layer includes depositing silicon oxide.
Claim 11
Dependent Claim
126 words
A flash memory cell structure, comprising: a substrate having a protruding section and a recessed section, wherein the protruding section has a sidewall and there is a substrate surface between the protruding section and the recessed section; a tunnel oxide layer over the substrate surface between the protruding section and the recessed section; a common drain terminal at a top end of the protruding section; a source terminal located in the substrate between the protruding section and the recessed section; a floating gate above the tunnel oxide and between the source terminal and the drain terminal; a dielectric layer above the floating gate; a shallow trench isolation structure in the recessed section; and a control gate between the dielectric layer and the shallow trench isolation structure.
Claim 12
Dependent Claim
126 words
A flash memory cell structure, comprising: a substrate having a protruding section and a recessed section, wherein the protruding section has a sidewall and there is a substrate surface between the protruding section and the recessed section; a tunnel oxide layer over the substrate surface between the protruding section and the recessed section; a common drain terminal at a top end of the protruding section; a source terminal located in the substrate between the protruding section and the recessed section; a floating gate above the tunnel oxide and between the source terminal and the drain terminal; a dielectric layer above the floating gate; a shallow trench isolation structure in the recessed section; and a control gate between the dielectric layer and the shallow trench isolation structure.
Claim 13
Dependent Claim
17 words
The structure of claim 10 , wherein a material for forming the floating gate includes doped polysilicon.
Claim 14
Dependent Claim
17 words
The structure of claim 10 , wherein a material for forming the control gate includes doped polysilicon.
Claim 15
Dependent Claim
18 words
The structure of claim 10 , wherein a material for forming the first dielectric layer includes silicon oxide.
References Cited (Backward Citations)
US5892257A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-02 | 2005-01-01 | 2005-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-02 | 2009-01-01 | 2009-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-02 | 2013-01-01 | 2013-07-03 | $7700.00 | Window Closed / Lapsed |