US6246089B1
Expired / Lapsed
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P-channel EEPROM devices
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2000-03-13
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Granted: 2001-06-12
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Expires: 2020-03-13
Abstract
Abstract A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
Inventors
- 👤 Yai-Fen Lin
- 👤 Shiou-Hann Liaw
- 👤 Di-Son Kuo
- 👤 Juang-Ke Yeh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
134 words
An FET semiconductor device including a doped silicon semiconductor substrate having a surface, said substrate being doped with an N type of dopant, including: a tunnel oxide layer over said substrate, a laminated floating gate electrode layer including an intermediate layer of N+ doped polysilicon over said tunnel oxide layer, an interelectrode dielectric layer over said floating gate electrode, a control gate electrode including a layer composed of P+ doped polysilicon over said interelectrode dielectric layer, said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode patterned into a gate electrode stack, a source region and a drain region in said surface of said substrate doped with a P type of dopant, said source region and said drain region being self-aligned with said gate electrode stack.
Claim 2
Dependent Claim
134 words
An FET semiconductor device including a doped silicon semiconductor substrate having a surface, said substrate being doped with an N type of dopant, including: a tunnel oxide layer over said substrate, a laminated floating gate electrode layer including an intermediate layer of N+ doped polysilicon over said tunnel oxide layer, an interelectrode dielectric layer over said floating gate electrode, a control gate electrode including a layer composed of P+ doped polysilicon over said interelectrode dielectric layer, said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode patterned into a gate electrode stack, a source region and a drain region in said surface of said substrate doped with a P type of dopant, said source region and said drain region being self-aligned with said gate electrode stack.
Claim 3
Dependent Claim
36 words
The device of claim 1 wherein said floating gate electrode layer is a laminated structure comprising: a lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an upper polysilicon layer.
Claim 4
Dependent Claim
38 words
The device of claim 1 wherein said source/drain dopant comprises P type dopant atoms of boron fluoride, BF 2 , having a concentration from about 1 E 18 atoms/cm 3 to about 1 E 20 atoms/cm 3 .
Claim 5
Dependent Claim
20 words
The device of claim 1 wherein said floating gate has a thickness from about 1,000 Å to about 1,200 Å.
Claim 6
Dependent Claim
69 words
The device of claim 1 wherein said floating gate electrode layer is a laminated structure comprising: a lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å.
Claim 7
Dependent Claim
52 words
The device of claim 1 wherein said floating gate electrode layer is a laminated structure comprising a lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an upper polysilicon layer, and said tunnel oxide layer has a thickness from about 90 Å to about 100 Å.
Claim 8
Dependent Claim
84 words
The device of claim 1 wherein said floating gate electrode layer is a laminated structure comprising a lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an upper polysilicon layer, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant atoms of boron fluoride, BF 2 , with a concentration from about 1 E 18 atoms/cm 3 to about 1 E 20 atoms/cm 3 .
Claim 9
Dependent Claim
117 words
The device of claim 1 wherein said floating gate electrode layer is a laminated structure comprising: a lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant atoms of boron fluoride, BF 2 , with a concentration from about 1 E 18 atoms/cm 3 to about 1 E 20 atoms/cm 3 .
Claim 10
Dependent Claim
148 words
The device of claim 1 wherein said floating gate electrode layer is a laminated structure comprising: a lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant atoms of boron fluoride, BF 21 with a concentration from about 1 E 18 atoms/cm 3 to about 1 E 20 atoms/cm 3 , and said substrate is doped by N type dopant comprising atoms of phosphorus, P, with a concentration from about 1 E 16 atoms/cm 3 to about 5 E 17 atoms/cm 3 .
Claim 11
Dependent Claim
140 words
An FET semiconductor device including a doped silicon semiconductor substrate having a surface, said substrate being doped with an N type of dopant, including: a tunnel oxide layer over said substrate, a laminated floating gate electrode layer including an intermediate layer of N+ doped polysilicon over said tunnel oxide layer between undoped layers of polysilicon, a interelectrode dielectric layer over said floating gate electrode, a control gate electrode including a layer composed of P+ doped polysilicon over said interelectrode dielectric layer, said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode being patterned into a gate electrode stack, a source region and a drain region in said surface of said substrate doped with a P type of dopant, said source region and said drain region being self-aligned with said gate electrode stack.
Claim 12
Dependent Claim
140 words
An FET semiconductor device including a doped silicon semiconductor substrate having a surface, said substrate being doped with an N type of dopant, including: a tunnel oxide layer over said substrate, a laminated floating gate electrode layer including an intermediate layer of N+ doped polysilicon over said tunnel oxide layer between undoped layers of polysilicon, a interelectrode dielectric layer over said floating gate electrode, a control gate electrode including a layer composed of P+ doped polysilicon over said interelectrode dielectric layer, said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode being patterned into a gate electrode stack, a source region and a drain region in said surface of said substrate doped with a P type of dopant, said source region and said drain region being self-aligned with said gate electrode stack.
Claim 13
Dependent Claim
205 words
In an FET semiconductor device including a doped silicon semiconductor substrate having a surface and doped with an N type of dopant, the improvement comprising: a tunnel oxide layer over said substrate, floating gate gate electrode layers comprising a laminated floating gate electrode including a lower undoped polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, comprising: a lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysillicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, an interelectrode dielectric layer over said floating gate electrode, a control gate electrode including a layer composed of P+ doped polysilicon over said interelectrode dielectric layer, said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode being patterned into a gate electrode stack, a source region and a drain region in said surface of said substrate doped with a P type of dopant, said source region and said drain region being self-aligned with said gate electrode stack.
Claim 14
Dependent Claim
205 words
In an FET semiconductor device including a doped silicon semiconductor substrate having a surface and doped with an N type of dopant, the improvement comprising: a tunnel oxide layer over said substrate, floating gate gate electrode layers comprising a laminated floating gate electrode including a lower undoped polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, comprising: a lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysillicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, an interelectrode dielectric layer over said floating gate electrode, a control gate electrode including a layer composed of P+ doped polysilicon over said interelectrode dielectric layer, said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode being patterned into a gate electrode stack, a source region and a drain region in said surface of said substrate doped with a P type of dopant, said source region and said drain region being self-aligned with said gate electrode stack.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-11 | 2004-12-11 | 2005-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-11 | 2008-12-11 | 2009-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-11 | 2012-12-11 | 2013-06-12 | $7700.00 | Window Closed / Lapsed |