US6236632B1
Expired / Lapsed
US
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Disk driver
Assignee: Toshiba Corp
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Filing: 1999-04-29
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Granted: 2001-05-22
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Expires: 2019-04-29
Abstract
Abstract Data read from a disk is input to an RF amplifier. An RF amplifier generates, based on bit data, an RF signal constituted by a plurality of components of mutually different frequencies. The RF amplifier determines a relation between the frequencies and gains on the basis of a control clock and adjusts the gains of respective components in the RF signals on the basis of the relation (equalize-processing). A PLL circuit has a first VCO and first frequency divider to generate a bit clock and generates, on the basis of an output signal of a data slice circuit, a first control voltage for controlling the first VCO. The first control voltage, being passed through a lowpass filter, is converted to a second control voltage for controlling a second VCO. The second VCO has an arrangement and characteristic substantially the same as those of the first VCO. A control clock for determining the peak position of the gain, that is, the characteristic of the RF amplifier, is generated based on an output clock of the second VCO.
Inventors
- 👤 Yasuhiro Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:50
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/02; G11B20/04; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G11B7/00; G11B7/004; G11B7/005; H03L7/0807; H03L7/085; H03L7/087; H04; H04N; H04N5/00; H04N5/76; H04N5/84; H04N5/85; G11B20/10; G11B20/14; G11B20/1403; H04N9/00; H04N9/79; H04N9/80; H04N9/804; H04N9/8042
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
156 words
A disk driver comprising: an equalizer, in regard to an RF signal constituted by a plurality of components of mutually different frequencies based on data read from a disk, determining a relation between the frequencies and gains based on a control clock, and performing equalize-processing by adjusting the gains of the components based on the relation; a data slice circuit converting the components to digital signals; a PLL circuit having a first VCO to generate a bit clock and generating a first control voltage for controlling the first VCO based on the digital signals; a lowpass filter generating a second control voltage based on the first control voltage; a second VCO controlled by the second control voltage and having an arrangement and characteristic substantially equal to those of the first VCO; and a feedback circuit generating the control clock based on a clock output from the second VCO and supplying the control clock to the equalizer.
Claim 2
Dependent Claim
156 words
A disk driver comprising: an equalizer, in regard to an RF signal constituted by a plurality of components of mutually different frequencies based on data read from a disk, determining a relation between the frequencies and gains based on a control clock, and performing equalize-processing by adjusting the gains of the components based on the relation; a data slice circuit converting the components to digital signals; a PLL circuit having a first VCO to generate a bit clock and generating a first control voltage for controlling the first VCO based on the digital signals; a lowpass filter generating a second control voltage based on the first control voltage; a second VCO controlled by the second control voltage and having an arrangement and characteristic substantially equal to those of the first VCO; and a feedback circuit generating the control clock based on a clock output from the second VCO and supplying the control clock to the equalizer.
Claim 3
Dependent Claim
39 words
A disk driver according to claim 1 , wherein the equalize-processing is performed by making the gains of high frequency-side components of the plurality of components higher than the gains of low frequency-side components of the plurality of components.
Claim 4
Dependent Claim
23 words
A disk driver according to claim 1 , wherein the equalizer shifts a peak position of the gain based on the control clock.
Claim 5
Dependent Claim
34 words
A disk driver according to claim 1 , further comprising a pickup for irradiating the disk with a laser beam and for generating the data based on a reflected laser beam from the disk.
Claim 6
Dependent Claim
41 words
A disk driver according to claim 4 , further comprising a servo control circuit which generates a signal for driving the pickup based on a servo control signal, the servo control signal being generated by the equalizer based on the data.
Claim 7
Dependent Claim
87 words
A disk driver according to claim 1 , further comprising: a disk motor for driving the disk; a synchronous signal separating circuit for generating a synchronous signal synchronous with a data rate based on the digital signals; and a disk motor control circuit for monitoring a rotation speed of the disk in a CAV mode, and setting the rotation speed of the disk substantially constant in the CAV mode, and for controlling the rotation speed of the disk based on the synchronous signal in a CLV mode.
Claim 8
Dependent Claim
25 words
A disk driver according to claim 1 , wherein the feedback circuit divides the clock output from the second VCO to output the control clock.
Claim 9
Dependent Claim
142 words
A disk driver comprising: an equalizer, in regard to an RF signal constituted by a plurality of components of mutually different frequencies based on data read from a disk, determining a relation between the frequencies and gains based on a control clock, and performing equalize-processing by adjusting the gains of the components based on the relation; a data slice circuit converting the components to digital signals; a PLL circuit having a VCO to generate a bit clock and generating a control voltage for controlling the VCO based on the digital signals; a feedback circuit generating the control clock based on either one of the bit clock and a clock having a predetermined frequency and supplying the control clock to the equalizer; and a selector supplying either one of the bit clock and the clock having the predetermined frequency to the feedback circuit.
Claim 10
Dependent Claim
142 words
A disk driver comprising: an equalizer, in regard to an RF signal constituted by a plurality of components of mutually different frequencies based on data read from a disk, determining a relation between the frequencies and gains based on a control clock, and performing equalize-processing by adjusting the gains of the components based on the relation; a data slice circuit converting the components to digital signals; a PLL circuit having a VCO to generate a bit clock and generating a control voltage for controlling the VCO based on the digital signals; a feedback circuit generating the control clock based on either one of the bit clock and a clock having a predetermined frequency and supplying the control clock to the equalizer; and a selector supplying either one of the bit clock and the clock having the predetermined frequency to the feedback circuit.
Claim 11
Dependent Claim
33 words
A disk driver according to claim 8 , wherein the feedback circuit includes a divider dividing one of the bit clock and the clock having the predetermined frequency to generate the control clock.
Claim 12
Dependent Claim
26 words
A disk driver according to claim 8 , wherein the clock having the predetermined frequency is obtained by dividing a clock output from a crystal oscillator.
Claim 13
Dependent Claim
39 words
A disk driver according to claim 8 , wherein the equalize-processing is performed by making the gains of high-frequency side components of the plurality of components higher than the gains of low-frequency side components of the plurality of components.
Claim 14
Dependent Claim
23 words
A disk driver according to claim 8 , wherein the equalizer shifts a peak position of the gains based on the control clock.
Claim 15
Dependent Claim
34 words
A disk driver according to claim 8 , further comprising a pickup for irradiating the disk with a laser beam and for generating the data based on a reflected laser beam from the disk.
Claim 16
Dependent Claim
41 words
A disk driver according to claim 13 , further comprising a servo control circuit which generates a signal for driving the pickup based on a servo control signal, the servo control signal being generated by the equalizer based on the data.
Claim 17
Dependent Claim
83 words
A disk driver according to claim 8 , further comprising: a disk motor for driving the disk; a synchronous signal separating circuit for generating a synchronous signal synchronous with a data rate based on the digital signals; and a disk motor control circuit for monitoring a rotation speed of the disk and setting the rotation speed of the disk substantially constant in the CAV mode, and for controlling the rotation speed of the disk based on the synchronous signal in a CLV mode.
Claim 18
Dependent Claim
53 words
A disk driver according to claim 8 , wherein the selector supplies the clock having the predetermined frequency to the feedback circuit when the equalize-processing by the equalizer is in an abnormal state and supplies the bit clock to the feedback circuit when the equalize-processing by the equalizer is in a normal state.
Claim 19
Dependent Claim
191 words
A disk driver comprising: an equalizer, in regard to an RF signal constituted by a plurality of components of mutually different frequencies based on data read from a disk, determining a relation between the frequencies and gains based on a control clock, and performing equalize-processing by adjusting the gains of the components based on the relation; a data slice circuit for converting the components to digital signals; a PLL circuit having a first VCO to generate a bit clock and generating a first control voltage for controlling the first VCO based on the digital signals; a lowpass filter generating a second control voltage based on the first control voltage; a second VCO controlled by the second control voltage and having an arrangement and characteristic substantially equal to those of the first VCO; a feedback circuit generating the control clock based on either one of a clock output from the second VCO and a clock having a predetermined frequency and supplying the control clock to the equalizer; and a selector supplying either one of the clock output from the second VCO and the clock having the predetermined frequency to the feedback circuit.
Claim 20
Dependent Claim
191 words
A disk driver comprising: an equalizer, in regard to an RF signal constituted by a plurality of components of mutually different frequencies based on data read from a disk, determining a relation between the frequencies and gains based on a control clock, and performing equalize-processing by adjusting the gains of the components based on the relation; a data slice circuit for converting the components to digital signals; a PLL circuit having a first VCO to generate a bit clock and generating a first control voltage for controlling the first VCO based on the digital signals; a lowpass filter generating a second control voltage based on the first control voltage; a second VCO controlled by the second control voltage and having an arrangement and characteristic substantially equal to those of the first VCO; a feedback circuit generating the control clock based on either one of a clock output from the second VCO and a clock having a predetermined frequency and supplying the control clock to the equalizer; and a selector supplying either one of the clock output from the second VCO and the clock having the predetermined frequency to the feedback circuit.
Claim 21
Dependent Claim
37 words
A disk driver according to claim 17 , wherein the feedback circuit includes a divider dividing one of the clock output from the second VCO and the clock having the predetermined frequency to generate the control clock.
Claim 22
Dependent Claim
26 words
A disk driver according to claim 17 , wherein the clock having the predetermined frequency is obtained by dividing a clock output from a crystal oscillator.
Claim 23
Dependent Claim
57 words
A disk driver according to claim 17 , wherein the selector supplies the clock having the predetermined frequency to the feedback circuit when the equalize-processing by the equalizer is in an abnormal state and supplies the clock output from the second VCO to the feedback circuit when the equalize-processing by the equalizer is in the normal state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-21 | 2004-11-20 | 2005-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-21 | 2008-11-20 | 2009-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-21 | 2012-11-20 | 2013-05-22 | $7700.00 | Window Closed / Lapsed |