US6235552B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip scale package and method for manufacturing the same using a redistribution substrate
Assignee: Samsung Electronics Co Ltd
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Filing: 2000-01-12
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Granted: 2001-05-22
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Expires: 2020-01-12
Abstract
Abstract A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate. Meanwhile, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnetion bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.
Inventors
- 👤 Yong Hwan Kwon
- 👤 Sa Yoon Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:28
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/69; H10W70/62; H10W70/63; H10W70/635; H10W72/00; H10W72/90; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W90/00; H10W90/701; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/743; H10W70/01; H10W70/05; H10W72/01; H10W72/012; H10W72/019; H10W72/01904; H10W72/01931; H10W72/01936; H10W72/0198; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/251; H10W72/29; H10W72/921; H10W72/922
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
131 words
A method for manufacturing a semiconductor package, comprising: providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads; attaching a semiconductor wafer, on which a plurality of integrated circuits and a plurality of chip pads are formed, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor wafer; forming a plurality of external terminals on the respective terminal pads of the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual semiconductor packages, each semiconductor package including an integrated circuit having a corresponding portion of the redistribution substrate attached thereon.
Claim 2
Independent Claim
131 words
A method for manufacturing a semiconductor package, comprising: providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads; attaching a semiconductor wafer, on which a plurality of integrated circuits and a plurality of chip pads are formed, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor wafer; forming a plurality of external terminals on the respective terminal pads of the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual semiconductor packages, each semiconductor package including an integrated circuit having a corresponding portion of the redistribution substrate attached thereon.
Claim 3
Dependent Claim
114 words
The method of claim 1 , wherein providing the redistribution substrate comprises: forming a first dielectric layer having a plurality of first openings on the substrate base; forming the terminal pads on the substrate base inside the first openings; forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads; forming a second dielectric layer on the patterned metal layer and the first dielectric layer, the second dielectric layer including a plurality of second openings; and forming the interconnection bumps on the patterned metal layer exposed through the second openings, wherein the interconnection bumps electrically connect to the respective terminal pads through the patterned metal layer.
Claim 4
Dependent Claim
35 words
The method of claim 1 , wherein forming the external terminals comprises: removing the substrate base so as to expose the terminal pads; and forming a plurality of protruding components on the respective terminal pads.
Claim 5
Dependent Claim
42 words
The method of claim 1 , wherein forming the external terminals comprises patterning the substrate base so that portions of the substrate base remain on the terminal pads, wherein the remaining portions of the substrate base are used as the external terminals.
Claim 6
Dependent Claim
28 words
The method of claim 1 , further comprising forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material.
Claim 7
Independent Claim
146 words
A method for manufacturing a semiconductor package, comprising: providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads; attaching a plurality of semiconductor integrated circuit chips, each of which has a plurality of chip pads formed thereon, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor chips; patterning the substrate base so that portions of the substrate base remain on the terminal pads, wherein the remaining portions of the substrate base are used as the external terminals; and separating the redistribution substrate so as to produce individual semiconductor packages, each of which includes an integrated circuit chip having a corresponding portion of the redistribution substrate attached thereon.
Claim 8
Independent Claim
146 words
A method for manufacturing a semiconductor package, comprising: providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads; attaching a plurality of semiconductor integrated circuit chips, each of which has a plurality of chip pads formed thereon, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor chips; patterning the substrate base so that portions of the substrate base remain on the terminal pads, wherein the remaining portions of the substrate base are used as the external terminals; and separating the redistribution substrate so as to produce individual semiconductor packages, each of which includes an integrated circuit chip having a corresponding portion of the redistribution substrate attached thereon.
Claim 9
Dependent Claim
110 words
The method of claim 6 , wherein providing the redistribution substrate comprises: forming a first dielectric layer having a plurality of first openings on the substrate base; forming the terminal pads on the substrate base inside the first openings; forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads; forming a second dielectric layer having a plurality of second openings on the patterned metal layer and the first dielectric layer; and forming the interconnection bumps on the patterned metal layer exposed through the second openings, wherein the interconnection bumps electrically connect to the respective terminal pads through the patterned metal layer.
Claim 10
Dependent Claim
29 words
The method of claim 6 , further comprising forming a buffer layer by filling a gap between the integrated circuit chips and the redistribution substrate with a dielectric material.
References Cited (Backward Citations)
US6071755A
Cited
US5895229A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-21 | 2004-11-20 | 2005-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-21 | 2008-11-20 | 2009-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-21 | 2012-11-20 | 2013-05-22 | $7700.00 | Window Closed / Lapsed |