US6233656B1
Expired / Lapsed
US
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Bandwidth optimization cache
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-12-22
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Granted: 2001-05-15
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Expires: 2017-12-22
Abstract
Abstract The present invention optimizes bus bandwidth utilization in an environment where bus accesses range in size from single word to multi-word burst accesses by prefetching and caching additional words when responding to a single word access request so that if the word is not found in cache, the single word request is converted into a multi-word fetch request. The present invention includes receiving a read request from a client; checking the contents of a cache to determine whether the cache contains information sought in the read request and returning the information from the cache if a cache hit results. If a cache miss results, a bus transaction is initiated by fetching a block of memory containing the information from a memory store, sending the information to the client, and caching the additional remaining information included with the fetched block of memory. The present invention may be implemented using a bus interface having a cache, and which is responsive to a read request received from the client. The bus interface is coupled to the client and to a bus, the cache returning information from the cache if a cache hit results, otherwise the bus interface fetching a block of memory containing the information from a memory store through the bus, sending the information to the client, caching remaining information within the fetched block of memory that was not requested in the read request, if a cache miss results in response to the read request.
Inventors
- 👤 Darren Jones
- 👤 Wei-Ting Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:05
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F2212/00; G06F2212/60; G06F2212/6022
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
191 words
A method for optimizing bus bandwidth utilization, the method comprising: determining if a single word of data is contained in a cache; completing a request-grant handshake between a memory bus interface and a memory controller if said single word of data is not contained in said cache; initiating a bus transaction by generating a request for said single word of data in said memory bus interface if said single word of data is not contained in said cache; generating a grant signal after waiting for a first latency time period for synchronization if said single word of data is not contained in said cache; producing a ready signal after waiting for a second latency time period for synchronization if said single word of data is not contained in said cache; creating a write-enable signal, said write-enable signal resulting in the transfer of eight contiguous words of data, at least one of which is said single word of data, from a memory store to said cache via said memory bus if said single word of data is not contained in said cache; and returning said single word of data from said cache.
Claim 2
Independent Claim
191 words
A method for optimizing bus bandwidth utilization, the method comprising: determining if a single word of data is contained in a cache; completing a request-grant handshake between a memory bus interface and a memory controller if said single word of data is not contained in said cache; initiating a bus transaction by generating a request for said single word of data in said memory bus interface if said single word of data is not contained in said cache; generating a grant signal after waiting for a first latency time period for synchronization if said single word of data is not contained in said cache; producing a ready signal after waiting for a second latency time period for synchronization if said single word of data is not contained in said cache; creating a write-enable signal, said write-enable signal resulting in the transfer of eight contiguous words of data, at least one of which is said single word of data, from a memory store to said cache via said memory bus if said single word of data is not contained in said cache; and returning said single word of data from said cache.
Claim 3
Dependent Claim
21 words
The method of claim 1 , wherein said single word of data is first in said eight contiguous words of data.
Claim 4
Dependent Claim
21 words
The method of claim 1 , wherein said single word of data is last in said eight contiguous words of data.
Claim 5
Independent Claim
203 words
A system for optimizing bus bandwidth utilization including: means for determining if a single word of data is contained in a cache; means for completing a request-grant handshake between a memory bus interface and a memory controller if said single word of data is not contained in said cache; means for initiating a bus transaction by generating a request for said single word of data in said memory bus interface if said single word of data is not contained in said cache; means for generating a grant signal after waiting for a first latency time period for synchronization if said single word of data is not contained in said cache; means for producing a ready signal after waiting for a second latency time period for synchronization if said single word of data is not contained in said cache; means for creating a write-enable signal, said write-enable signal resulting in the transfer of eight contiguous words of data, at least one of which is said single word of data, from a memory store to said cache via said memory bus if said single word of data is not contained in said cache; and means for returning said single word of data from said cache.
Claim 6
Independent Claim
203 words
A system for optimizing bus bandwidth utilization including: means for determining if a single word of data is contained in a cache; means for completing a request-grant handshake between a memory bus interface and a memory controller if said single word of data is not contained in said cache; means for initiating a bus transaction by generating a request for said single word of data in said memory bus interface if said single word of data is not contained in said cache; means for generating a grant signal after waiting for a first latency time period for synchronization if said single word of data is not contained in said cache; means for producing a ready signal after waiting for a second latency time period for synchronization if said single word of data is not contained in said cache; means for creating a write-enable signal, said write-enable signal resulting in the transfer of eight contiguous words of data, at least one of which is said single word of data, from a memory store to said cache via said memory bus if said single word of data is not contained in said cache; and means for returning said single word of data from said cache.
Claim 7
Dependent Claim
21 words
The system of claim 4 , wherein said single word of data is first in said eight contiguous words of data.
Claim 8
Dependent Claim
21 words
The system of claim 4 , wherein said single word of data is last in said eight contiguous words of data.
Claim 9
Dependent Claim
211 words
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for optimizing bus bandwidth utilization, the method including: determining if a single word of data is contained in a cache; completing a request-grant handshake between a memory bus interface and a memory controller if said single word of data is not contained in said cache; initiating a bus transaction by generating a request for said single word of data in said memory bus interface if said single word of data is not contained in said cache; generating a grant signal after waiting for a first latency time period for synchronization if said single word of data is not contained in said cache; producing a ready signal after waiting for a second latency time period for synchronization if said single word of data is not contained in said cache; creating a write-enable signal, said write-enable signal resulting in the transfer of eight contiguous words of data, at least one of which is said single word of data, from a memory store to said cache via said memory bus if said single word of data is not contained in said cache; and returning said single word of data from said cache.
Claim 10
Dependent Claim
211 words
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for optimizing bus bandwidth utilization, the method including: determining if a single word of data is contained in a cache; completing a request-grant handshake between a memory bus interface and a memory controller if said single word of data is not contained in said cache; initiating a bus transaction by generating a request for said single word of data in said memory bus interface if said single word of data is not contained in said cache; generating a grant signal after waiting for a first latency time period for synchronization if said single word of data is not contained in said cache; producing a ready signal after waiting for a second latency time period for synchronization if said single word of data is not contained in said cache; creating a write-enable signal, said write-enable signal resulting in the transfer of eight contiguous words of data, at least one of which is said single word of data, from a memory store to said cache via said memory bus if said single word of data is not contained in said cache; and returning said single word of data from said cache.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-14 | 2004-11-13 | 2005-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-14 | 2008-11-13 | 2009-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-14 | 2012-11-13 | 2013-05-15 | $7700.00 | Window Closed / Lapsed |