US6184751B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier circuit
Assignee: Google Technology Holdings LLC
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Filing: 1998-08-17
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Granted: 2001-02-06
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Expires: 2018-08-17
Abstract
Abstract An amplifier circuit ( 20 ) uses a series transistor ( 38 ) to couple the output of an amplifier ( 26 ) to a tuned circuit load ( 40 ) and to act as a variable resistance. In one embodiment for a multi-band receiver, multiple series transistors ( 38, 42 ) are switched for connecting different tuned circuits ( 40, 44 ) to the amplifier's output, and an activated one of the series transistors receives a gate voltage that varies its resistance so as to achieve gain control. An activated series transistors can also provide a resistance that stabilizes the amplifier ( 26 ).
Inventors
- 👤 John Robert Siomkos
- 👤 Edgar Herbert Callaway, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:42
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/007; H03G3/00; H03G3/02; H03G3/14; H03G3/18; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
172 words
A gain-controlled amplifier circuit for a multi-band receiver, comprising: an amplifier having an output; at least a first tuned circuit tuned to a first band of frequencies and a second tuned circuit tuned to a second band of frequencies; a first series transistor coupled between the output of the amplifier and the first tuned circuit; a second series transistor coupled between the output of the amplifier and the second tuned circuit, the first and second series transistors each having a gate and a source, and an activated one of the series transistors creating a series path of variable resistance between the output of the amplifier and a tuned circuit; band selection circuitry coupled to the first series transistor and to the second series transistor for selectively activating one of the first and second series transistors; and gain control circuitry coupled to an activated series transistor for varying a voltage Vgs between the gate and the source of the activated series transistor so as to vary the resistance of the activated series transistor.
Claim 2
Dependent Claim
172 words
A gain-controlled amplifier circuit for a multi-band receiver, comprising: an amplifier having an output; at least a first tuned circuit tuned to a first band of frequencies and a second tuned circuit tuned to a second band of frequencies; a first series transistor coupled between the output of the amplifier and the first tuned circuit; a second series transistor coupled between the output of the amplifier and the second tuned circuit, the first and second series transistors each having a gate and a source, and an activated one of the series transistors creating a series path of variable resistance between the output of the amplifier and a tuned circuit; band selection circuitry coupled to the first series transistor and to the second series transistor for selectively activating one of the first and second series transistors; and gain control circuitry coupled to an activated series transistor for varying a voltage Vgs between the gate and the source of the activated series transistor so as to vary the resistance of the activated series transistor.
Claim 3
Dependent Claim
51 words
A gain-controlled amplifier circuit as set forth in claim 1 wherein the gain control circuitry includes: a source of AGC current; and current mirror circuitry, including first and second interruptable current paths, receiving the AGC current and causing the voltage Vgs to vary in response to variations in the AGC current.
Claim 4
Dependent Claim
31 words
A gain-controlled amplifier circuit as set forth in claim 2 wherein the band selection circuitry interrupts one of the first and second interruptable current paths and completes the other current path.
Claim 5
Dependent Claim
50 words
A gain-controlled amplifier circuit as set forth in claim 1 , wherein the gain control circuitry causes the voltage Vgs to vary between a turn-on value and a turn-off value, and wherein an activated series transistor acts as a low resistance when the voltage Vgs is at the turn-on value.
Claim 6
Dependent Claim
46 words
A gain-controlled amplifier circuit as set forth in claim 4 , including parasitic capacitance coupled to the output of the amplifier, and wherein the low resistance provided by the activated series transistor causes the parasitic capacitance to be effectively coupled in parallel with the tuned circuit.
Claim 7
Dependent Claim
223 words
A gain-controlled amplifier circuit for a multi-band receiver, comprising: a cascode amplifier having an output; parasitic capacitance coupled to the output of the amplifier; at least a first tuned circuit tuned to a first band of frequencies and a second tuned circuit tuned to a second band of frequencies; a first series transistor coupled between the output of the amplifier and the first tuned circuit; a second series transistor coupled between the output of the amplifier and the second tuned circuit, wherein the first and second series transistors each has a gate and a source, and wherein an activated one of the series transistors creates a series path of variable resistance between the output of the amplifier and a selected tuned circuit; band selection circuitry coupled to the first series transistor and to the second series transistor for selectively activating one of the first and second series transistors; a source of AGC current; and current mirror circuitry receiving the AGC current for applying a variable voltage to the gate of the activated series transistor, the variable voltage varying in response to variations in the AGC current, and wherein the activated series transistor acts as a low resistance when the variable voltage is at a low value to thereby cause the parasitic capacitance to be effectively coupled in parallel with the selected tuned circuit.
Claim 8
Dependent Claim
223 words
A gain-controlled amplifier circuit for a multi-band receiver, comprising: a cascode amplifier having an output; parasitic capacitance coupled to the output of the amplifier; at least a first tuned circuit tuned to a first band of frequencies and a second tuned circuit tuned to a second band of frequencies; a first series transistor coupled between the output of the amplifier and the first tuned circuit; a second series transistor coupled between the output of the amplifier and the second tuned circuit, wherein the first and second series transistors each has a gate and a source, and wherein an activated one of the series transistors creates a series path of variable resistance between the output of the amplifier and a selected tuned circuit; band selection circuitry coupled to the first series transistor and to the second series transistor for selectively activating one of the first and second series transistors; a source of AGC current; and current mirror circuitry receiving the AGC current for applying a variable voltage to the gate of the activated series transistor, the variable voltage varying in response to variations in the AGC current, and wherein the activated series transistor acts as a low resistance when the variable voltage is at a low value to thereby cause the parasitic capacitance to be effectively coupled in parallel with the selected tuned circuit.
Claim 9
Dependent Claim
224 words
An amplifier circuit for a multi-band receiver, comprising: an amplifier having an output; at least a first tuned circuit tuned to a first band of frequencies and a second tuned circuit tuned to a second band of frequencies; a first series transistor coupled between the output of the amplifier and the first tuned circuit; a second series transistor coupled between the output of the amplifier and the second tuned circuit, wherein each of the series transistors has a gate, wherein an activated one of the series transistors creates a series path between the output of the amplifier and a tuned circuit, and wherein the first and second series transistors each exhibit a resistance that varies with the amplitude of a voltage received at its gate; band selection circuitry coupled to the first series transistor and to the second series transistor for selectively activating one of the first and second series transistors; a source of control current having at least a first maximum current level for the first band of frequencies and at least a second maximum current level for the second band of frequencies; and current mirror circuitry receiving the control current for supplying, to the gate of the activated series transistor, a voltage selected to cause the activated series transistor to exhibit a resistance that depends on the band of frequencies being received.
Claim 10
Dependent Claim
224 words
An amplifier circuit for a multi-band receiver, comprising: an amplifier having an output; at least a first tuned circuit tuned to a first band of frequencies and a second tuned circuit tuned to a second band of frequencies; a first series transistor coupled between the output of the amplifier and the first tuned circuit; a second series transistor coupled between the output of the amplifier and the second tuned circuit, wherein each of the series transistors has a gate, wherein an activated one of the series transistors creates a series path between the output of the amplifier and a tuned circuit, and wherein the first and second series transistors each exhibit a resistance that varies with the amplitude of a voltage received at its gate; band selection circuitry coupled to the first series transistor and to the second series transistor for selectively activating one of the first and second series transistors; a source of control current having at least a first maximum current level for the first band of frequencies and at least a second maximum current level for the second band of frequencies; and current mirror circuitry receiving the control current for supplying, to the gate of the activated series transistor, a voltage selected to cause the activated series transistor to exhibit a resistance that depends on the band of frequencies being received.
References Cited (Backward Citations)
US2737628A
Cited
US4757276A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-06 | 2004-08-07 | 2005-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-06 | 2008-08-07 | 2009-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-06 | 2012-08-07 | 2013-02-06 | $7700.00 | Window Closed / Lapsed |