US6180935B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic range extension of CCD imagers
Assignee: BAE Systems Information and Electronic Systems Integration Inc
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Filing: 1999-01-25
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Granted: 2001-01-30
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Expires: 2019-01-25
Abstract
Abstract Dynamic range extension (DRE) is achieved in CCD imagers with charge overflow structures by varying the potential V G on the gate electrodes of the pixel signal charge wells during charge integration. The wells are formed to function with the charge overflow structures, e.g., vertical overflow drains, VODs, a) to control the signal charge spreading due to illumination overload and/or b) as a means for the control of signal integration time. Two different V G levels are applied to the gate electrodes, the lower of the two levels V G -LOW is applied for a long duration and the higher level V G -HIGH is applied for a shorter duration during charge integration. At low levels of incident illumination on the CCD surface, charge signals are integrated without saturation, but, at levels of very intense illumination during the period with voltage V G -LOW on the gates, the pixel wells will saturate before the end of charge integration, resulting in the vertical overflow drain (VOD) operating to dump excess charge to the substrate. With the subsequent imposition of V G -HIGH for a short time period near the end of the integration interval, pixel well saturation is delayed and signals corresponding to high intensity are not lost. Consequently, imposing V G -HIGH for a short time period near the end of the integration interval (a) increases pixel charge storage capacity and (b) shortens the exposure time, which combination allows high intensity signal information to be integrated without loss by saturation.
Inventors
- 👤 Kenneth A. Hoagland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:54
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/62; H04N25/621; H04N25/622; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/158
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
186 words
A method of achieving dynamic range extension (DRE) in a CCD imager exposed to combined low and high intensity illumination, said imager having a CCD imaging surface for converting incident illumination into electrical charge, and gate electrodes acting on said surface having a voltage V G applied thereto to form pixel signal charge wells at well sites below said surface during charge integration, comprising the steps of: imposing a voltage V G -LOW on said gate electrodes at the pixel signal charge integration well sites, said voltage V G -LOW being of a level that results in signal charge wells above the reference signal level for automatic light control used in CCD imager systems and of a time duration equal to a large percentage of the total time of charge integration; and then imposing a voltage V G -HIGH on said gate electrodes at the pixel signal charge integration well sites, said voltage V G -HIGH being of a level that is above the level of voltage V G -LOW and of a comparatively short time duration with respect to the total time of charge integration.
Claim 2
Independent Claim
186 words
A method of achieving dynamic range extension (DRE) in a CCD imager exposed to combined low and high intensity illumination, said imager having a CCD imaging surface for converting incident illumination into electrical charge, and gate electrodes acting on said surface having a voltage V G applied thereto to form pixel signal charge wells at well sites below said surface during charge integration, comprising the steps of: imposing a voltage V G -LOW on said gate electrodes at the pixel signal charge integration well sites, said voltage V G -LOW being of a level that results in signal charge wells above the reference signal level for automatic light control used in CCD imager systems and of a time duration equal to a large percentage of the total time of charge integration; and then imposing a voltage V G -HIGH on said gate electrodes at the pixel signal charge integration well sites, said voltage V G -HIGH being of a level that is above the level of voltage V G -LOW and of a comparatively short time duration with respect to the total time of charge integration.
Claim 3
Dependent Claim
41 words
A method as in claim 1 wherein voltage V G -LOW is set at a level to achieve a maximum pixel well capacity equal to from 25% to 50% of the full 100% well capacity achieved with voltage V G -HIGH.
Claim 4
Dependent Claim
36 words
A method as in claim 1 wherein the reference signal level for automatic light control used in CCD imager systems, which the voltage V G -LOW is set above, is ¼ to ½ full well saturation.
Claim 5
Dependent Claim
28 words
A method as in claim 1 wherein voltage V G -LOW is imposed for a time duration greater than about 90% of the total time of charge integration.
Claim 6
Dependent Claim
18 words
A method as in claim 1 wherein said pixel signal charge integration well sites contain overflow drains (OD).
Claim 7
Dependent Claim
16 words
A method as in claim 5 wherein said overflow drains (OD) comprise vertical overflow drains (VOD).
Claim 8
Independent Claim
212 words
A system for achieving dynamic range extension (DRE) in a CCD imager having a CCD imaging surface for converting incident illumination into electrical charge, and gate electrodes acting on said surface having a voltage V G applied thereto to form pixel signal charge wells at well sites below said surface during charge integration, comprising: means for imposing a voltage V G -LOW on said gate electrodes at the pixel signal charge integration well sites during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -LOW being of a level that results in signal charge wells above the reference signal level for automatic light control used in CCD imager systems and of a time duration equal to a large percentage of the total time of charge integration; and means for imposing a voltage V G -HIGH on said gate electrodes at the pixel signal charge integration well sites during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -HIGH being of a level that is above the level of said voltage V G -LOW and being imposed for a comparatively short time duration with respect to the total time of charge integration following the imposition of said voltage V G -LOW.
Claim 9
Independent Claim
212 words
A system for achieving dynamic range extension (DRE) in a CCD imager having a CCD imaging surface for converting incident illumination into electrical charge, and gate electrodes acting on said surface having a voltage V G applied thereto to form pixel signal charge wells at well sites below said surface during charge integration, comprising: means for imposing a voltage V G -LOW on said gate electrodes at the pixel signal charge integration well sites during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -LOW being of a level that results in signal charge wells above the reference signal level for automatic light control used in CCD imager systems and of a time duration equal to a large percentage of the total time of charge integration; and means for imposing a voltage V G -HIGH on said gate electrodes at the pixel signal charge integration well sites during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -HIGH being of a level that is above the level of said voltage V G -LOW and being imposed for a comparatively short time duration with respect to the total time of charge integration following the imposition of said voltage V G -LOW.
Claim 10
Dependent Claim
43 words
A system as in claim 7 further comprising means for setting voltage V G -LOW at a level to achieve a maximum pixel well capacity equal to from 25% to 50% of the full 100% well capacity achieved with voltage V G -HIGH.
Claim 11
Dependent Claim
54 words
A system as in claim 7 wherein said means for imposing voltage V G -LOW in setting the level of voltage V G -LOW above the reference signal level for automatic light control used in CCD imager systems, sets the voltage V G -LOW at a level of ¼ to ½ full well saturation.
Claim 12
Dependent Claim
30 words
A system as in claim 7 further comprising means for imposing voltage V G -LOW for a time duration greater than about 90% of the total time of charge integration.
Claim 13
Dependent Claim
18 words
A system as in claim 7 wherein said pixel signal charge integration well sites contain overflow drains (OD).
Claim 14
Dependent Claim
16 words
A system as in claim 7 wherein said overflow drains (OD) comprise vertical overflow drains (VOD).
Claim 15
Independent Claim
274 words
A system for extending the dynamic range of a CCD imager with overflow drains (OD) incorporated into its pixel structures containing pixel signal charge integration wells therein, said pixel structures comprising: a substrate of one conductivity type; a region of opposite conductivity type on said substrate, said region being shaped to collect excess signal charge spilling from said pixel signal charge integration wells; a region of said one conductivity type deposited in the upper surface of said pixel structure containing said pixel signal charge integration wells; two channel stop regions of strong opposite conductivity type deposited on opposite sides of said region of said one conductivity type; and a gate electrode on a dielectric layer located above said regions on said upper surface of said well portion; and said system further comprising: means for imposing a voltage V G -LOW on said gate electrode during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -LOW being of a level that results in signal charge wells above the reference signal level for automatic light control used in CCD imager systems and of a time duration that is a large percentage of the total time of charge integration; and means for imposing a voltage V G -HIGH on said gate electrode during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -HIGH being of a level that is above the level of said voltage V G -LOW and being imposed for a comparatively short time duration with respect to the total time of charge integration following the imposition of said voltage V G -LOW.
Claim 16
Independent Claim
274 words
A system for extending the dynamic range of a CCD imager with overflow drains (OD) incorporated into its pixel structures containing pixel signal charge integration wells therein, said pixel structures comprising: a substrate of one conductivity type; a region of opposite conductivity type on said substrate, said region being shaped to collect excess signal charge spilling from said pixel signal charge integration wells; a region of said one conductivity type deposited in the upper surface of said pixel structure containing said pixel signal charge integration wells; two channel stop regions of strong opposite conductivity type deposited on opposite sides of said region of said one conductivity type; and a gate electrode on a dielectric layer located above said regions on said upper surface of said well portion; and said system further comprising: means for imposing a voltage V G -LOW on said gate electrode during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -LOW being of a level that results in signal charge wells above the reference signal level for automatic light control used in CCD imager systems and of a time duration that is a large percentage of the total time of charge integration; and means for imposing a voltage V G -HIGH on said gate electrode during the incidence of high intensity illumination on said CCD imaging surface, said voltage V G -HIGH being of a level that is above the level of said voltage V G -LOW and being imposed for a comparatively short time duration with respect to the total time of charge integration following the imposition of said voltage V G -LOW.
Claim 17
Dependent Claim
42 words
A system as in claim 13 further comprising means for setting voltage V G -LOW at a level to achieve a maximum pixel well capacity equal to 25% to 50% of the full 100% well capacity achieved with voltage V G -HIGH.
Claim 18
Dependent Claim
54 words
A system as in claim 13 wherein said means for imposing voltage V G -LOW in setting the level of voltage V G -LOW above the reference signal level for automatic light control used in CCD imager systems, sets the voltage V G -LOW at a level of ¼ to ½ full well saturation.
Claim 19
Dependent Claim
30 words
A system as in claim 13 further comprising means for imposing voltage V G -LOW for a time duration greater than about 90% of the total time of charge integration.
Claim 20
Dependent Claim
16 words
A system as in claim 13 wherein said overflow drain comprises a vertical overflow drain (VOD).
References Cited (Backward Citations)
USRE34802E
Cited
US6040570A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |