US6177787B1
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Circuits and methods for controlling timing and slope compensation in switching regulators
Assignee: Analog Devices International ULC
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Filing: 1999-08-26
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Granted: 2001-01-23
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Expires: 2019-08-26
Abstract
Abstract Circuits and methods for controlling timing and slope compensation in switching regulators are provided. These circuits and methods include a timing control circuit that controls the timing of the switching of one or more switching regulator output stages so that the switching occurs at evenly spaced time intervals, and a slope compensation circuit that produces a slope compensation signal having a waveform that need not match the waveform of any oscillator signal, nor that need have the same period as the oscillator signal. Timing control is performed by dividing a master clock signal using a T flip-flop and a “rolling clock” (or “Johnson counter”) to produce 2N clock phase signals. Slope compensation is provided by generating a slope compensation signal using decoding logic, a digital-to-analog converter (DAC), and an integrator.
Inventors
- 👤 Stephen W. Hobrecht
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:27
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156; H02M3/158; H02M3/1584
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
98 words
A control circuit that controls switch timing in a plurality of switching regulator output stages and generates at least one slope compensation waveform, comprising: a timing circuit, coupled to each of the output stages, that generates a plurality of phase signals from a clock signal, wherein each of the phase signals controls the switch timing of a different one of the output stages; and a slope compensation waveform generating circuit that receives at least two of the phase signals from the timing circuit and that generates a slope compensation waveform for at least one of the output stages.
Claim 2
Dependent Claim
98 words
A control circuit that controls switch timing in a plurality of switching regulator output stages and generates at least one slope compensation waveform, comprising: a timing circuit, coupled to each of the output stages, that generates a plurality of phase signals from a clock signal, wherein each of the phase signals controls the switch timing of a different one of the output stages; and a slope compensation waveform generating circuit that receives at least two of the phase signals from the timing circuit and that generates a slope compensation waveform for at least one of the output stages.
Claim 3
Dependent Claim
16 words
The control circuit of claim 1 wherein the timing circuit comprises a plurality of D flip-flops.
Claim 4
Dependent Claim
26 words
The control circuit of claim 1 wherein the timing circuit comprises a frequency divider that divides a higher frequency clock signal to provide the clock signal.
Claim 5
Dependent Claim
14 words
The control circuit of claim 3 wherein the frequency divider is a T flip-flop.
Claim 6
Dependent Claim
61 words
The control circuit of claim 1 wherein the timing circuit further comprises a quadrature-phase output circuit that provides a quadrature-phase output signal having a rising edge that occurs at a time between a first signal rising time of a first adjacent one of the phase signals and a second signal rising time of a second adjacent one of the phase signals.
Claim 7
Dependent Claim
55 words
The control circuit of claim 5 wherein the quadrature-phase output circuit comprises: a D flip-flop that receives an input phase signal from the first adjacent one of the phase signals and that provides the quadrature-phase output signal; and an inverter that inverts the clock signal to provide an inverted clock signal to the D flip-flop.
Claim 8
Dependent Claim
91 words
The control circuit of claim 1 , wherein the slope compensation waveform generating circuit comprises: decoder circuitry that receives a clock signal and the at least two of the phase signals, and that provides a plurality of counter bit outputs and a reset signal; a digital-to-analog converter that produces an output signal in response to the counter bit outputs provided by the decoder circuitry; and an integrator that integrates the output signal produced by the digital-to-analog converter to produce the slope compensation waveform and that is reset by the reset signal.
Claim 9
Dependent Claim
49 words
The control circuit of claim 7 , wherein the decoder circuitry comprises: a counter that counts the clock signal to provide the counter bit outputs and that is reset by the reset signal; and a logic device that logically combines the output phase signals to produce the reset signal.
Claim 10
Dependent Claim
18 words
The control circuit of claim 8 wherein the logic device is an AND gate with an inverted input.
Claim 11
Dependent Claim
32 words
The control circuit of claim 7 wherein the digital-to-analog converter comprises a plurality of current sources that provide a current flow in response to the counter bit outputs of the decoder circuitry.
Claim 12
Dependent Claim
48 words
The control circuit of claim 10 wherein the digital-to-analog converter further comprises a plurality of switches that are responsive to the counter bit outputs and that control when the plurality of current sources provide the current flow in response to the counter bit outputs of the decoder circuitry.
Claim 13
Dependent Claim
57 words
The control circuit of claim 7 wherein the integrator comprises: a capacitor that stores charge in response to the output signal produced by the digital-to-analog converter; an operational amplifier that produces the slope compensation signal in response to the charge stored in the capacitor; and a switch that discharges the capacitor in response to the reset signal.
Claim 14
Dependent Claim
26 words
The control circuit of claim 7 further comprising a voltage controlled current source that provides a slope compensation current in response to the slope compensation signal.
Claim 15
Independent Claim
95 words
A method for controlling a timing of switching signals and slope compensation waveforms of a plurality of switching regulator output stages comprising: receiving an input clock signal from a clock source; providing a plurality of output phase signals, wherein each of the plurality of output phase signals is used to control the switching of a unique one of the plurality of switching regulator output stages; and generating a corresponding slope compensation waveform for at least one of the plurality of switching regulator output stages using at least two of the plurality of output phase signals.
Claim 16
Independent Claim
95 words
A method for controlling a timing of switching signals and slope compensation waveforms of a plurality of switching regulator output stages comprising: receiving an input clock signal from a clock source; providing a plurality of output phase signals, wherein each of the plurality of output phase signals is used to control the switching of a unique one of the plurality of switching regulator output stages; and generating a corresponding slope compensation waveform for at least one of the plurality of switching regulator output stages using at least two of the plurality of output phase signals.
Claim 17
Dependent Claim
22 words
The method of claim 14 further comprising: reducing a master clock signal using a frequency divider to provide the input clock signal.
Claim 18
Dependent Claim
57 words
The method of claim 14 further comprising: providing a quadrature-phase output signal having a rising edge that occurs at a time between a first signal rising time of a first adjacent one of the plurality of output phase signals and a second signal rising time of a second adjacent one of the plurality of output phase signals.
Claim 19
Dependent Claim
70 words
The method of claim 16 wherein the providing of the quadrature-phase output signal comprises: receiving an input phase signal from the first adjacent one of the plurality of output phase signals; inverting the input clock signal to provide an inverted input clock signal; and generating the quadrature-phase output signal so that the quadrature-phase output signal matches the input phase signal at each rising edge of the inverted input clock signal.
Claim 20
Independent Claim
70 words
A method for generating a slope compensation signal for a switching regulator output stage, comprising: receiving an input clock signal and a plurality of phase input signals; providing a plurality of counter bit outputs and a reset signal; producing an output signal in response to the counter bit outputs; integrating the output signal to produce the slope compensation signal; and resetting the output signal in response to the reset signal.
Claim 21
Independent Claim
70 words
A method for generating a slope compensation signal for a switching regulator output stage, comprising: receiving an input clock signal and a plurality of phase input signals; providing a plurality of counter bit outputs and a reset signal; producing an output signal in response to the counter bit outputs; integrating the output signal to produce the slope compensation signal; and resetting the output signal in response to the reset signal.
Claim 22
Dependent Claim
57 words
The method of claim 18 , wherein the providing of the plurality of counter bit outputs and the reset signal comprises: counting the input clock signal to provide the counter bit outputs; resetting the counter bit outputs in response to the reset signal; and logically combining the plurality of phase input signals to produce the reset signal.
Claim 23
Dependent Claim
42 words
The method of claim 19 wherein the logically combining comprises: inverting one of the plurality of phase input signals to produce an inverted signal; and performing a logical AND on the inverted signal and another of the plurality of phase input signals.
Claim 24
Dependent Claim
31 words
The method of claim 18 wherein the producing of the output signal in response to the counter bit outputs comprises providing a current flow in response to the counter bit outputs.
Claim 25
Dependent Claim
38 words
The method of claim 21 wherein the producing of the output signal in response to the counter bit outputs further comprises switching the current flow using a plurality of switches that are responsive to the counter bit outputs.
Claim 26
Dependent Claim
62 words
The method of claim 18 wherein the integrating of the output signal to produce the slope compensation signal and the resetting of the output signal in response to the reset signal comprises: storing charge in response to the output signal; producing the slope compensation signal in response to the charge stored; and discharging the charge stored in response to the reset signal.
Claim 27
Dependent Claim
19 words
The method of claim 18 further comprising providing a slope compensation current in response to the slope compensation signal.
References Cited (Backward Citations)
No citation records indexed.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-23 | 2004-07-24 | 2005-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-23 | 2008-07-24 | 2009-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-23 | 2012-07-24 | 2013-01-23 | $7700.00 | Window Closed / Lapsed |