US6172902B1
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US
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Non-volatile magnetic random access memory
Assignee: École Polytechnique Fédérale de Lausanne
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Filing: 1999-08-13
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Granted: 2001-01-09
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Expires: 2019-08-13
Abstract
Abstract A non-volatile random access memory (NVRAM) of the type with magnetoresistive memory elements ( 1 ) connected by sets of non-intersecting conductor sense lines ( 3, 4 ) which define the address of each memory element ( 1 ) and are connectable to a magnetic write/read recording unit. The memory elements are a plurality of magnetoresistive submicron dots or wires ( 1 ) embedded in a membrane ( 2 ) through which the submicron dots or wires extend. The sets of non-intersecting conductor sense lines ( 3, 4 ) are connected to the opposite ends of the submicron dots or wires ( 1 ) on opposite sides of the membrane. Each magnetoresistive submicron dot or wire ( 1 ) is composed of ferromagnetic material or a combination of ferromagnetic and non-ferromagnetic materials having at least two magnetic states (“0”; “1”), writeable by passing at an appropriate external field a writing current pulse (i w ) in its conductor lines ( 3, 4, 5 ) sufficient to switch its magnetic states and readable by passing a an AC or DC current (i r ) in its conductor lines below the level for switching its magnetic states.
Inventors
- 👤 Jean-Eric Wegrowe
- 👤 Jean-Philippe Ansermet
- 👤 Scott E. Gilbert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/16; G11C11/161; H; H10; H10B; H10B61/00; B; B82; B82Y; B82Y10/00; G11C2213/00; G11C2213/70; G11C2213/81
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
190 words
A non-volatile random access memory comprising a plurality of magnetoresistive memory elements connected by sets of non-intersecting conductor sense lines, the non-intersecting conductor sense lines defining the address of each memory element and being connectable to a magnetic write/read recording unit for writing and reading the magnetic state (“0”, “1”) of each memory element by passing current in its conductor sense lines; wherein the memory elements are a plurality of magnetoresistive submicron dots or wires embedded in a membrane through which the submicron dots or wires extend, the sets of non-intersecting conductor sense lines being connected to the opposite ends of the submicron dots or wires on opposite sides of the membrane; each magnetoresistive submicron dot or wire being composed of ferromagnetic material or a combination of ferromagnetic and non-ferromagnetic materials having at least two magnetic states (“0”; “1”), writeable and readable absent an induced magnetic field therein by passing there through an electric current, writeable by passing a writing current pulse in its conductor lines sufficient to switch its magnetic states and readable by passing a current in its conductor lines below the level for switching its magnetic states.
Claim 2
Dependent Claim
190 words
A non-volatile random access memory comprising a plurality of magnetoresistive memory elements connected by sets of non-intersecting conductor sense lines, the non-intersecting conductor sense lines defining the address of each memory element and being connectable to a magnetic write/read recording unit for writing and reading the magnetic state (“0”, “1”) of each memory element by passing current in its conductor sense lines; wherein the memory elements are a plurality of magnetoresistive submicron dots or wires embedded in a membrane through which the submicron dots or wires extend, the sets of non-intersecting conductor sense lines being connected to the opposite ends of the submicron dots or wires on opposite sides of the membrane; each magnetoresistive submicron dot or wire being composed of ferromagnetic material or a combination of ferromagnetic and non-ferromagnetic materials having at least two magnetic states (“0”; “1”), writeable and readable absent an induced magnetic field therein by passing there through an electric current, writeable by passing a writing current pulse in its conductor lines sufficient to switch its magnetic states and readable by passing a current in its conductor lines below the level for switching its magnetic states.
Claim 3
Dependent Claim
28 words
The random access memory of claim 1 , wherein the submicron dots or wires are composed of ferromagnetic material or of ferromagnetic/non-ferromagnetic metal/ferromagnetic multilayers or a ferromagnetic/dielectric/ferromagnetic junction.
Claim 4
Dependent Claim
30 words
The random access memory of claim 1 , wherein the submicron dots or wires have a diameter from 10 to 100 nm and a length from 200 to 10,000 nm.
Claim 5
Dependent Claim
23 words
The random access memory of claim 1 , comprising up to 10 9 submicron dots or wires per cm 2 of the membrane.
Claim 6
Dependent Claim
31 words
The random access memory of claim 1 , wherein the membrane is bonded to or integral with a silicon wafer substrate including integrated circuitry for processing the reading and writing currents.
Claim 7
Dependent Claim
27 words
The random access memory of claim 5 , wherein the integrated circuitry comprises one integrated circuit element for each memory element comprising a submicron dot or wire.
Claim 8
Dependent Claim
27 words
The random access memory of claim 1 , wherein the membrane is a track-etched polymer membrane, a porous aluminum oxide membrane, or a porous silicon oxide membrane.
Claim 9
Dependent Claim
46 words
The random access memory of claim 1 , wherein a ferromagnetic or anti-ferromagnetic layer is provided on the top or bottom of the membrane in contact with the dot or wire to induce a bias exchange field for switching the memory element at weak applied field.
Claim 10
Dependent Claim
49 words
The random access memory of claim 1 , wherein a ferromagnetic layer is provided on the top or bottom of the membrane and separated from the dot or wire by a thin layer of non-ferromagnetic material, to polarize the conduction electrons and amplify the action of the writing current.
Claim 11
Dependent Claim
57 words
A method of producing the random access memory of claim 1 , wherein nickel or other ferromagnetic elements or alloys possessing adequate magnetoresistive characteristics are deposited into the pores of a porous membrane template using a layer of resist having a predefined pattern of apertures corresponding to the memory elements each comprising a submicron dot or wire.
Claim 12
Dependent Claim
15 words
A data storage device comprising a non-volatile random access memory according to claim 1 .
Claim 13
Dependent Claim
60 words
A method of writing and reading data in a random access memory according to claim 1 , wherein the writing comprises supplying current pulses to change the magnetic state of the memory elements which each comprise a submicron dot or wire, and the reading comprises passing a lower AC or DC current to determine the resistance of the memory elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-09 | 2004-07-10 | 2005-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-09 | 2008-07-10 | 2009-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-09 | 2012-07-10 | 2013-01-09 | $7700.00 | Window Closed / Lapsed |