US6166775A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video signal sampling circuit and an image display apparatus including the same
Assignee: JVCKenwood Corp
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Filing: 1998-09-02
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Granted: 2000-12-26
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Expires: 2018-09-02
Abstract
Abstract A video signal sampling circuit searches the optimum sampling frequency and phase of the sampling clock signal by detecting level changing points in the sampled video signal in the horizontal direction with the sampling frequency varied every predetermined phase. The saturated maximum count of the level changing point provides the optimum sampling frequency and optimum phase of the sampling clock signal. The video signal sampling circuit automatically sets the optimum sampling frequency and phase of the sampling clock signal in accordance with the result of searching. The video display including the video signal sampling circuit is also disclosed.
Inventors
- 👤 Hisatoshi Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:58
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/003; G09G5/006; G09G5/008; H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; H04N; H04N9/00; H04N9/64; H04N9/641; H03; H03L; H03L7/00; H04N5/00; H04N5/74; H04N5/7416; H04N5/7441; H04N2005/745; H04N5/44; H04N5/46; H04N9/12; H04N9/31; H04N9/3102
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
238 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal; counting means for counting said changing points for a predetermined interval; control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means; and detection means responsive to said horizontal synchronizing signal and a vertical synchronizing signal of said video signal for detecting the number of pixels of said video signal in the vertical direction, wherein said control means further determines a range of said frequency control data in accordance with the detected number of pixels and successively changes said frequency control data within said range to detect said saturated maximum count value of said counting means.
Claim 2
Dependent Claim
238 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal; counting means for counting said changing points for a predetermined interval; control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means; and detection means responsive to said horizontal synchronizing signal and a vertical synchronizing signal of said video signal for detecting the number of pixels of said video signal in the vertical direction, wherein said control means further determines a range of said frequency control data in accordance with the detected number of pixels and successively changes said frequency control data within said range to detect said saturated maximum count value of said counting means.
Claim 3
Dependent Claim
39 words
The video signal sampling circuit as claimed in claim 1, wherein said changing point detection means comprises a line memory for storing said level changing points every line of said video signal through an OR operation between said lines.
Claim 4
Dependent Claim
110 words
A video signal sampling circuit as claimed in claim 1, wherein said video signal includes color signals, said sampling means samples said color signals in response to the sampling signal and outputs sampled color signals, said changing point detection means detects level changing points of the sampled color signals, said changing point detection means further comprises OR operation means for effecting an OR operation among detected level changing points of the sampled color signals at the same horizontal positions for the same horizontal scanning period, and said counting means counts said changing points from an output of said OR operation means for said horizontal scanning period as said predetermined interval.
Claim 5
Dependent Claim
187 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal; counting means for counting said changing points for a predetermined interval wherein said counting means counts said level changing points every frame in response to a vertical synchronizing signal of said video signal; and control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means.
Claim 6
Dependent Claim
187 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal; counting means for counting said changing points for a predetermined interval wherein said counting means counts said level changing points every frame in response to a vertical synchronizing signal of said video signal; and control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means.
Claim 7
Dependent Claim
39 words
The video signal sampling circuit as claimed in claim 4, wherein said changing point detection means comprises a line memory for storing said level changing points every line of said video signal through an OR operation between said lines.
Claim 8
Dependent Claim
194 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal wherein said changing point detection means comprises a line memory for storing said level changing points every line of said video signal through an OR operation between said lines; counting means for counting said changing points for a predetermined interval; and control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means.
Claim 9
Dependent Claim
194 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal wherein said changing point detection means comprises a line memory for storing said level changing points every line of said video signal through an OR operation between said lines; counting means for counting said changing points for a predetermined interval; and control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means.
Claim 10
Dependent Claim
242 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal, said changing point detection means comprising first to third changing point detection circuits responsive to red, green, and blue signals included in said video signal, an OR gate for effecting an OR operation among outputs of said first to third changing point detection circuits, and a line memory responsive to a vertical synchronizing signal for storing said level changing points from said OR gate every line of said video signal through an OR operation between said lines; counting means for counting said changing points for a predetermined interval; and control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means.
Claim 11
Dependent Claim
242 words
A video signal sampling circuit comprising: sampling clock signal generation means responsive to a horizontal synchronizing signal of a video signal for generating a sampling clock signal of which a frequency and phase to said horizontal synchronizing signal are respectively controlled in accordance with frequency control data and phase control data; sampling means for sampling said video signal in response to said sampling clock signal and outputting the sampled video signal; changing point detection means for detecting level changing points in the sampled video signal, said changing point detection means comprising first to third changing point detection circuits responsive to red, green, and blue signals included in said video signal, an OR gate for effecting an OR operation among outputs of said first to third changing point detection circuits, and a line memory responsive to a vertical synchronizing signal for storing said level changing points from said OR gate every line of said video signal through an OR operation between said lines; counting means for counting said changing points for a predetermined interval; and control means responsive to a command signal for detecting saturated maximum count value of said counting means with said frequency control data and said phase control data successively changed, determining values of said frequency control data and said phase control data at said saturated maximum count value, and continuously supplying the determined frequency control data and the determined phase control data to said sampling clock signal generation means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |