Method for manufacturing a semiconductor device and an exposure mask used therefor

Claim 1

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask in which repeat pattern portions having shifter portions and non-shifter portions alternately and repeatedly arranged and non-repeat pattern portions having irregularly arranged patterns are separately formed in a plurality of regions of one exposure mask, light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions; preparing a semiconductor wafer having a plurality of chip areas; aligning a pattern on one of the plurality of regions of the exposure mask with each of the plurality of chip areas on the semiconductor wafer; effecting an exposing process in an illuminating condition corresponding to the pattern on the one region, each time after aligning the pattern with each of the plurality of chip areas; aligning a pattern on a different one of the plurality of regions on the exposure mask with each of the plurality of chip areas on the semiconductor wafer; and effecting an exposing process in another illuminating condition corresponding to the pattern on the different one region, each time after aligning the pattern with each of the plurality of chip areas, wherein the step of effecting an exposing process corresponding to the pattern on the different one of the plurality of regions on the exposure mask is repeatedly effected until the exposing process for all of the plurality of regions of the exposure mask is completed.

Claim 2

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask in which repeat pattern portions having shifter portions and non-shifter portions alternately and repeatedly arranged and non-repeat pattern portions having irregularly arranged patterns are separately formed in a plurality of regions of one exposure mask, light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions; preparing a semiconductor wafer having a plurality of chip areas; aligning a pattern on one of the plurality of regions of the exposure mask with each of the plurality of chip areas on the semiconductor wafer; effecting an exposing process in an illuminating condition corresponding to the pattern on the one region, each time after aligning the pattern with each of the plurality of chip areas; aligning a pattern on a different one of the plurality of regions on the exposure mask with each of the plurality of chip areas on the semiconductor wafer; and effecting an exposing process in another illuminating condition corresponding to the pattern on the different one region, each time after aligning the pattern with each of the plurality of chip areas, wherein the step of effecting an exposing process corresponding to the pattern on the different one of the plurality of regions on the exposure mask is repeatedly effected until the exposing process for all of the plurality of regions of the exposure mask is completed.

Claim 7

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask in which repeat pattern portions having shifter portions and non-shifter portions alternately and repeatedly arranged and non-repeat pattern portions having irregularly arranged patterns are separately formed in a plurality of regions of one exposure mask, light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions; preparing a semiconductor wafer having a plurality of chip areas; aligning a pattern on one of the plurality of regions of the exposure mask with one of the plurality of chip areas on the semiconductor wafer; exposing the pattern on the one region in an illuminating condition corresponding to the pattern on the one region; aligning a pattern on a different one of the plurality of regions on the exposure mask with the one of the plurality of chip areas on the semiconductor wafer; and exposing the pattern on the different region in another illuminating condition corresponding to the pattern on the different one region, wherein the step of exposing the pattern on the different one of the plurality of regions on the exposure mask is repeatedly effected until an operation of exposing all of the plurality of regions of the exposure mask for the one of the plurality of chip areas is completed and then an exposure operation cycle is sequentially repeated for the plurality of chip areas.

Claim 8

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask in which repeat pattern portions having shifter portions and non-shifter portions alternately and repeatedly arranged and non-repeat pattern portions having irregularly arranged patterns are separately formed in a plurality of regions of one exposure mask, light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions; preparing a semiconductor wafer having a plurality of chip areas; aligning a pattern on one of the plurality of regions of the exposure mask with one of the plurality of chip areas on the semiconductor wafer; exposing the pattern on the one region in an illuminating condition corresponding to the pattern on the one region; aligning a pattern on a different one of the plurality of regions on the exposure mask with the one of the plurality of chip areas on the semiconductor wafer; and exposing the pattern on the different region in another illuminating condition corresponding to the pattern on the different one region, wherein the step of exposing the pattern on the different one of the plurality of regions on the exposure mask is repeatedly effected until an operation of exposing all of the plurality of regions of the exposure mask for the one of the plurality of chip areas is completed and then an exposure operation cycle is sequentially repeated for the plurality of chip areas.

Claim 13

A method for manufacturing a semiconductor device comprising the steps of: preparing a plurality of first exposure masks having repeat pattern portions with shifter portions and non-shifter portions alternately and repeatedly arranged and a plurality of second exposure masks having non-repeat pattern portions with irregularly arranged patterns, where light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions; preparing a plurality of semiconductor wafers each having a plurality of chip areas; sequentially aligning one pattern in the plurality of first exposure masks with the plurality of chip areas on the plurality of semiconductor wafers; exposing the pattern in the plurality of first exposure masks in an illuminating condition corresponding to the pattern; sequentially aligning one pattern in the plurality of second exposure masks with the plurality of chip areas on the plurality of semiconductor wafers; and exposing the pattern in the plurality of second exposure masks in another illuminating condition corresponding to the pattern, wherein the step of exposing the pattern in the plurality of first exposure masks and the step of exposing the pattern in the plurality of second exposure masks are repeatedly effected by the number of times respectively equal to the number of the first exposure masks and number of the second exposure masks.

Claim 14

A method for manufacturing a semiconductor device comprising the steps of: preparing a plurality of first exposure masks having repeat pattern portions with shifter portions and non-shifter portions alternately and repeatedly arranged and a plurality of second exposure masks having non-repeat pattern portions with irregularly arranged patterns, where light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions; preparing a plurality of semiconductor wafers each having a plurality of chip areas; sequentially aligning one pattern in the plurality of first exposure masks with the plurality of chip areas on the plurality of semiconductor wafers; exposing the pattern in the plurality of first exposure masks in an illuminating condition corresponding to the pattern; sequentially aligning one pattern in the plurality of second exposure masks with the plurality of chip areas on the plurality of semiconductor wafers; and exposing the pattern in the plurality of second exposure masks in another illuminating condition corresponding to the pattern, wherein the step of exposing the pattern in the plurality of first exposure masks and the step of exposing the pattern in the plurality of second exposure masks are repeatedly effected by the number of times respectively equal to the number of the first exposure masks and number of the second exposure masks.

Claim 21

A method for manufacturing a semiconductor device comprising the steps of: preparing a semiconductor wafer having a plurality of chip areas; preparing an exposure mask formed to cause repeat pattern portions having shifter portions and non-shifter portions alternately and repeatedly arranged and non-repeat pattern portions having irregularly arranged patterns to be projected on different ones of the plurality of chip areas on the semiconductor wafer, light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions and a diffraction grating pattern being provided in a region corresponding to the non-repeat pattern portions; and simultaneously exposing the repeat pattern portions and the non-repeat pattern portions of the exposure mask to the different ones of the plurality of chip areas of the semiconductor wafers, wherein the repeat pattern portions and the non-repeat pattern portions are exposed to preset areas among substantially all of the plurality of chip areas by repeatedly effecting the exposing step to expose the repeat pattern portions onto substantially all of the plurality of chip areas.

Claim 22

A method for manufacturing a semiconductor device comprising the steps of: preparing a semiconductor wafer having a plurality of chip areas; preparing an exposure mask formed to cause repeat pattern portions having shifter portions and non-shifter portions alternately and repeatedly arranged and non-repeat pattern portions having irregularly arranged patterns to be projected on different ones of the plurality of chip areas on the semiconductor wafer, light having passed through one of the shifter portions having a phase difference with respect to light having passed through one of the non-shifter portions adjacent to the one of the shifter portions and a diffraction grating pattern being provided in a region corresponding to the non-repeat pattern portions; and simultaneously exposing the repeat pattern portions and the non-repeat pattern portions of the exposure mask to the different ones of the plurality of chip areas of the semiconductor wafers, wherein the repeat pattern portions and the non-repeat pattern portions are exposed to preset areas among substantially all of the plurality of chip areas by repeatedly effecting the exposing step to expose the repeat pattern portions onto substantially all of the plurality of chip areas.

Claim 24

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask in which a plurality of island-form opening patterns are regularly arranged and an optical path difference of approximately 1/2 of a wave length λ of an exposure light is provided for each of adjacent opening patterns; forming a semiconductor element on a semiconductor substrate; forming an insulating film on the semiconductor substrate having the semiconductor element formed thereon; forming a positive type resist layer on the insulating film; exposing the resist layer via a pattern of the exposure mask and developing the same to form a resist pattern; selectively etching the insulation film to form trenches by using the resist pattern as a mask; and filling a wiring material in the trenches of the insulating film.

Claim 25

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask in which a plurality of island-form opening patterns are regularly arranged and an optical path difference of approximately 1/2 of a wave length λ of an exposure light is provided for each of adjacent opening patterns; forming a semiconductor element on a semiconductor substrate; forming an insulating film on the semiconductor substrate having the semiconductor element formed thereon; forming a positive type resist layer on the insulating film; exposing the resist layer via a pattern of the exposure mask and developing the same to form a resist pattern; selectively etching the insulation film to form trenches by using the resist pattern as a mask; and filling a wiring material in the trenches of the insulating film.

Claim 26

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask having an alternating phase shift region and a non-alternating phase shift region; exposing a first portion of each of a plurality of chip areas on a semiconductor wafer with only said phase shift region of said exposure mask in a first illuminating condition; and exposing a second portion, different than said first portion, of each of said plurality of chip areas with only said non-alternating phase shift region of said exposure mask in a second illuminating condition different from said first illumination condition.

Claim 27

A method for manufacturing a semiconductor device comprising the steps of: preparing an exposure mask having an alternating phase shift region and a non-alternating phase shift region; exposing a first portion of each of a plurality of chip areas on a semiconductor wafer with only said phase shift region of said exposure mask in a first illuminating condition; and exposing a second portion, different than said first portion, of each of said plurality of chip areas with only said non-alternating phase shift region of said exposure mask in a second illuminating condition different from said first illumination condition.