PLL circuit

Claim 2

A PLL circuit comprising: a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal and at least one other signal; and mask means for either transmitting or blocking the phase error signal in accordance with said at least one other signal and the signal to be compared.

Claim 3

A PLL circuit comprising: a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal; and mask means for either transmitting or blocking the phase error signal using a signal obtained by delaying the reference signal or the reproduction signal by an arbitrary time.

Claim 4

A PLL circuit comprising: a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal; and mask means for either transmitting or blocking the phase error signal using a signal obtained by delaying the reference signal or the reproduction signal by an arbitrary time.

Claim 5

A circuit according to claim 1, wherein the phase comparator includes a first shift register comprising cascade-connected flip-flops to which the reference signal or the reproduction signal is input, and the mask means includes a second shift register comprising cascade-connected flip-flops to which an output from the first shift register is input, and wherein the mask means further includes a first exclusive OR gate which receives an output from an arbitrary one of the flip-flops constituting the first shift register and an output from an arbitrary one of the flip-flops constituting the second shift register, and a second exclusive OR gate which receives an output from an arbitrary one of the flip-flops constituting the second shift register and an output from another one of the flip-flops constituting the second shift register, and wherein the mask means either transmits or blocks the phase error signal based on output signals from the first and second exclusive OR gates.

Claim 6

A circuit according to claim 1, wherein the phase comparator includes a first shift register comprising cascade-connected flip-flops to which the reference signal or the reproduction signal is input, and an exclusive OR gate which receives an output from one of the flip-flops constituting the first shift register and the reference signal or the reproduction signal and outputs the phase error signal, and wherein said mask means includes a toggle flip-flop for receiving the phase error signal and outputting a control signal based on which the phase error signal is transmitted or blocked.

Claim 7

A PLL circuit comprising: a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal; and mask means for either transmitting or blocking the phase error signal in accordance with a signal obtained by frequency-dividing the phase error signal.

Claim 8

A PLL circuit comprising: a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal; and mask means for either transmitting or blocking the phase error signal in accordance with a signal obtained by frequency-dividing the phase error signal.

Claim 9

A PLL circuit comprising: a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal and at least one other signal, wherein the reference signal or the reproduction signal is input to the phase comparator through a frequency divider, and the phase error signal is transmitted or blocked in accordance with said at least one other signal and the signal to be compared.

Claim 10

A PLL circuit comprising: a phase comparator for detecting a phase difference between a reference signal having a predetermined frequency or a reproduction signal having signal change points at irregular time intervals and a signal to be compared and outputting a phase error signal and at least one other signal, wherein the reference signal or the reproduction signal is input to the phase comparator through a frequency divider, and the phase error signal is transmitted or blocked in accordance with said at least one other signal and the signal to be compared.

Claim 11

A circuit according to claim 1, wherein said mask means blocks part of the phase error signal when said PLL circuit is locked and transmits the phase error signal when said PLL circuit is not locked.

Claim 12

A circuit according to claim 1, wherein a period for blocking the phase error output is set based on an external control signal.

Claim 13

A PLL circuit comprising: a phase comparator for detecting a phase difference between a signal to be compared and a reproduction signal having signal change points at irregular time intervals and outputting a phase error signal, the reproduction signal being generated from a recording medium at a time interval not less than a minimum time interval Tmin from a fall to a rise of the reproduction signal based on a sampling interval T; and mask means for blocking the phase error signal using a time interval of (Tmin-0.5 T) to (Tmin-1.5 T).

Claim 14

A PLL circuit comprising: a phase comparator for detecting a phase difference between a signal to be compared and a reproduction signal having signal change points at irregular time intervals and outputting a phase error signal, the reproduction signal being generated from a recording medium at a time interval not less than a minimum time interval Tmin from a fall to a rise of the reproduction signal based on a sampling interval T; and mask means for blocking the phase error signal using a time interval of (Tmin-0.5 T) to (Tmin-1.5 T).

Claim 15

A circuit according to claim 2, wherein said mask means blocks part of the phase error signal when said PLL circuit is locked and transmits the phase error signal when said PLL circuit is not locked.

Claim 16

A circuit according to claim 5, wherein said mask means blocks part of the phase error signal when said PLL circuit is locked and transmits the phase error signal when said PLL circuit is not locked.

Claim 17

A circuit according to claim 2, wherein a period for blocking the phase error output is set based on an external control signal.

Claim 18

A circuit according to claim 5, wherein a period for blocking the phase error output is set based on an external control signal.