US6150862A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stable delay buffer
Assignee: Intel Corp
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Filing: 1998-10-15
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Granted: 2000-11-21
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Expires: 2018-10-15
Abstract
Abstract An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.
Inventors
- 👤 Omer Vikinski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:05
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/00078; H03K2005/00123; H03K2005/0013; H03K2005/00143
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
201 words
A circuit comprising: a driver circuit configured to output a signal; a load circuit coupled to the output of the driver circuit; and an active load circuit coupled to an output of the driver circuit, the active load circuit configured to actively adjust the slew rate of the signal wherein the active load circuit comprises: a capacitive load circuit; and a variable impedance circuit coupled between the driver circuit and the capacitive load circuit, the variable impedance circuit configured to adjust the slew rate in response to changes in fabrication process and operating conditions wherein the variable impedance circuit comprises: a first and a second nMOS transistor coupled between the output of the driver circuit and the capacitive load circuit; a first and a second pMOS transistor coupled between the output of the driver circuit and the capacitive load circuit, wherein a gate of the first nMOS transistor and a gate of the first pMOS transistor are coupled to an output of the load circuit; and an inverter having an input coupled to the output of the first load circuit, and an output coupled to a gate of the second nMOS transistor and to a gate of the second pMOS transistor.
Claim 2
Dependent Claim
201 words
A circuit comprising: a driver circuit configured to output a signal; a load circuit coupled to the output of the driver circuit; and an active load circuit coupled to an output of the driver circuit, the active load circuit configured to actively adjust the slew rate of the signal wherein the active load circuit comprises: a capacitive load circuit; and a variable impedance circuit coupled between the driver circuit and the capacitive load circuit, the variable impedance circuit configured to adjust the slew rate in response to changes in fabrication process and operating conditions wherein the variable impedance circuit comprises: a first and a second nMOS transistor coupled between the output of the driver circuit and the capacitive load circuit; a first and a second pMOS transistor coupled between the output of the driver circuit and the capacitive load circuit, wherein a gate of the first nMOS transistor and a gate of the first pMOS transistor are coupled to an output of the load circuit; and an inverter having an input coupled to the output of the first load circuit, and an output coupled to a gate of the second nMOS transistor and to a gate of the second pMOS transistor.
Claim 3
Dependent Claim
40 words
The circuit of claim 1 wherein the capacitive load circuit comprises: a nMOS capacitor coupled between a second voltage source and the variable impedance circuit; and a pMOS capacitor coupled between a first voltage source and the variable impedance circuit.
Claim 4
Dependent Claim
19 words
The circuit of claim 1 further comprising a first load circuit coupled to the output of the driver circuit.
Claim 5
Dependent Claim
18 words
The circuit of claim 1 wherein the driver circuit is a complementary metal oxide semiconductor (CMOS) driver circuit.
Claim 6
Dependent Claim
15 words
The circuit of claim 3 wherein the first load circuit is a CMOS load circuit.
Claim 7
Dependent Claim
24 words
The circuit of claim 3 wherein the driver circuit is a CMOS drive circuit and the first load circuit is a CMOS load circuit.
Claim 8
Dependent Claim
227 words
A circuit comprising: a driver circuit configured to output a signal; a first load circuit coupled to an output of the driver circuit; and an active load circuit coupled the output of the driver circuit and an output from the first load circuit, the active load circuit being configured to actively adjust the slew rate of the signal in response to an output signal from the first load circuit wherein the active load circuit comprises: a capacitive load circuit; and a variable impedance circuit coupled between the driver circuit and the capacitive load circuit, the variable impedance circuit configured to adjust the slew rate in response to changes in fabrication process and operating conditions wherein the variable impedance circuit comprises: a first and a second nMOS transistor coupled between the output of the driver circuit and the capacitive load circuit; a first and a second pMOS transistor coupled between the output of the driver circuit and the capacitive load circuit, wherein a gate of the first nMOS transistor and a gate of the first pMOS transistor are coupled to an output of the first load circuit; and an inverter with an input coupled to the output of the first load circuit, wherein an inverted output of the inverter is coupled to a gate of the second nMOS transistor and to a gate of the second pMOS transistor.
Claim 9
Dependent Claim
227 words
A circuit comprising: a driver circuit configured to output a signal; a first load circuit coupled to an output of the driver circuit; and an active load circuit coupled the output of the driver circuit and an output from the first load circuit, the active load circuit being configured to actively adjust the slew rate of the signal in response to an output signal from the first load circuit wherein the active load circuit comprises: a capacitive load circuit; and a variable impedance circuit coupled between the driver circuit and the capacitive load circuit, the variable impedance circuit configured to adjust the slew rate in response to changes in fabrication process and operating conditions wherein the variable impedance circuit comprises: a first and a second nMOS transistor coupled between the output of the driver circuit and the capacitive load circuit; a first and a second pMOS transistor coupled between the output of the driver circuit and the capacitive load circuit, wherein a gate of the first nMOS transistor and a gate of the first pMOS transistor are coupled to an output of the first load circuit; and an inverter with an input coupled to the output of the first load circuit, wherein an inverted output of the inverter is coupled to a gate of the second nMOS transistor and to a gate of the second pMOS transistor.
Claim 10
Dependent Claim
40 words
The circuit of claim 7 wherein the capacitive load circuit comprises: a nMOS capacitor coupled between a second power connection and the variable impedance circuit; and a pMOS capacitor coupled between a first power connection and the variable impedance circuit.
Claim 11
Dependent Claim
18 words
The circuit of claim 7 wherein the driver circuit is a complementary metal oxide semiconductor (CMOS) driver circuit.
Claim 12
Dependent Claim
15 words
The circuit of claim 7 wherein the first load circuit is a CMOS load circuit.
Claim 13
Dependent Claim
24 words
The circuit of claim 7 wherein the driver circuit is a CMOS drive circuit and the first load circuit is a CMOS load circuit.
References Cited (Backward Citations)
US5650740A
Cited
US5793238A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-21 | 2004-05-22 | 2004-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-21 | 2008-05-22 | 2008-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-21 | 2012-05-22 | 2012-11-21 | $7700.00 | Window Closed / Lapsed |