US6134137A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Rom-embedded-DRAM
Assignee: Micron Technology Inc
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Filing: 1998-07-31
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Granted: 2000-10-17
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Expires: 2018-07-31
Abstract
Abstract A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only "1" or to the wordline of an adjacent cell to create a read only "0".
Inventors
- 👤 Casey R. Kurth
- 👤 Scott J. Derner
- 👤 Patrick J. Mullarkey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:44
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; G; G11; G11C; G11C11/00; G11C11/005; G11C11/21; G11C11/24; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H10B12/30; H10B12/48; H10B12/488; H10B20/00; H10B20/27; H10B20/30
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
38 words
A memory circuit comprising: at least one bit line; at least one wordline; and a plurality of memory cells including at least one ROM cell having a capacitor always in electrical contact with said at least one wordline.
Claim 2
Dependent Claim
38 words
A memory circuit comprising: at least one bit line; at least one wordline; and a plurality of memory cells including at least one ROM cell having a capacitor always in electrical contact with said at least one wordline.
Claim 3
Dependent Claim
31 words
The memory circuit of claim 1 wherein said capacitor is in electrical contact with the wordline of said ROM cell such that said ROM cell is programmed as a read-only "1".
Claim 4
Dependent Claim
36 words
The memory circuit of claim 1 wherein said capacitor is in electrical contact with a wordline of a memory cell other than said ROM cell such that said ROM cell is programmed as a read-only "0".
Claim 5
Dependent Claim
13 words
The memory circuit of claim 1 further comprising at least one DRAM cell.
Claim 6
Dependent Claim
14 words
The memory circuit of claim 4 wherein said capacitor is over said bit line.
Claim 7
Dependent Claim
13 words
The memory circuit of claim 4 wherein said capacitor is a stacked capacitor.
Claim 8
Dependent Claim
13 words
The memory circuit of claim 6 wherein said capacitor is a container capacitor.
Claim 9
Dependent Claim
53 words
A ROM-embedded-DRAM memory circuit comprising: at least one DRAM cell having a bit line, a wordline, and a capacitor; and at least one ROM cell having a bit line, a wordline, and a capacitor, wherein said capacitor of said ROM cell is always in electrical contact with the wordline of said ROM cell.
Claim 10
Dependent Claim
53 words
A ROM-embedded-DRAM memory circuit comprising: at least one DRAM cell having a bit line, a wordline, and a capacitor; and at least one ROM cell having a bit line, a wordline, and a capacitor, wherein said capacitor of said ROM cell is always in electrical contact with the wordline of said ROM cell.
Claim 11
Dependent Claim
22 words
The ROM-embedded-DRAM memory circuit of claim 8 wherein said electrical contact is through a conductive plug disposed between said capacitor and wordline.
Claim 12
Dependent Claim
29 words
The ROM-embedded-DRAM memory circuit of claim 8, wherein the capacitor of said ROM cell is in electrical contact with a wordline other than the wordline of said ROM cell.
Claim 13
Dependent Claim
21 words
The memory circuit of claim 10 wherein said electrical contact is through a conductive plug disposed between said capacitor and wordline.
Claim 14
Dependent Claim
18 words
The ROM-embedded-DRAM memory circuit of claim 8 wherein said at least one bit line is above said capacitors.
Claim 15
Dependent Claim
14 words
The ROM-embedded-DRAM memory circuit of claim 12 wherein said capacitors are above said wordlines.
Claim 16
Dependent Claim
27 words
The ROM-embedded-DRAM memory circuit of claim 8 further comprising pheripheral circuitry, wherein said ROM cells are controlled by the same peripheral circuitry which controls said DRAM cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-17 | 2004-04-17 | 2004-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-17 | 2008-04-17 | 2008-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-17 | 2012-04-17 | 2012-10-17 | $7700.00 | Window Closed / Lapsed |