US6122735A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fault resilient boot circuit using ring counter
Assignee: Intel Corp
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Filing: 1998-05-21
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Granted: 2000-09-19
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Expires: 2018-05-21
Abstract
Abstract A fault resilient circuit, having a ring counter, that boots a multi-device system, such as multi-processor computer system. A timer accepts start timer and system operational signals and produces a system fail signal. A ring counter accepts the system fail signal, and the ring counter produces a plurality of device control signals. With such an arrangement, when enabling all of the devices substantially simultaneously does not produce a working system, the boot circuit can for, example, enable all but one of the devices and determine if the system operates correctly with all but one of the devices enabled. If the system does not operate correctly with all but one of the devices enabled, a single device in the system can be enabled and it is determined if the system operates correctly with a single device enabled.
Inventors
- 👤 Gregory J. Steiert
- 👤 Bassam N. Elkhoury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1417; G06F15/00; G06F15/16; G06F15/177
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
63 words
A fault resilient boot circuit, comprising: a system status determination unit accepting a start timer signal and a system operational signal and producing a system fail signal; and a ring counter accepting the fail signal, said ring counter producing a plurality of device control signals and comprising an n-bit register having said system fail signal coupled to said n-bit register's clock input signal.
Claim 2
Dependent Claim
63 words
A fault resilient boot circuit, comprising: a system status determination unit accepting a start timer signal and a system operational signal and producing a system fail signal; and a ring counter accepting the fail signal, said ring counter producing a plurality of device control signals and comprising an n-bit register having said system fail signal coupled to said n-bit register's clock input signal.
Claim 3
Dependent Claim
46 words
The fault resilient boot circuit of claim 1, wherein said system status determination unit comprises: a timer accepting the start timer signal and producing a time-out signal; and a logic device accepting the time-out signal and the system operational signal and producing the system fail signal.
Claim 4
Dependent Claim
16 words
The fault resilient boot circuit of claim 2, wherein said logic device is a NOR gate.
Claim 5
Dependent Claim
58 words
The fault resilient boot circuit of claim 1, wherein each time the system fail signal is produced, said ring counter selectively enables all but one of the device control signals, a different device control signal being not enabled each time, and then selectively enables a single device control signal, a different device control signal being enabled each time.
Claim 6
Dependent Claim
17 words
The fault resilient boot circuit of claim 1, wherein the device control signals are processor control signals.
Claim 7
Dependent Claim
31 words
The fault resilient boot circuit of claim 1, wherein said n-bit register having an output of at least one register being coupled to an input of at least one other register.
Claim 8
Dependent Claim
99 words
The fault resilient boot circuit of claim 1, wherein said n-bit register has eight input signals D1 to D8 and eight output signals Q1 to Q8; and wherein Q1 is coupled to D2, Q2 is coupled to D3, Q3 is coupled to D4, Q5 is coupled to D6, Q6 is coupled to D7, Q7 is coupled to D1 through an inverter, Q4 is coupled to a NOR gate, Q8 is coupled to the NOR gate through an inverter, the output signal from the NOR gate is coupled to D5 through an inverter, and D8 is coupled to a "1."
Claim 9
Dependent Claim
22 words
The fault resilient boot circuit of claim 7, wherein the output signals Q4 to Q7 are said ring counter's device control signals.
Claim 10
Dependent Claim
41 words
The fault resilient boot circuit of claim 8, wherein the four device control signals cycle through the following states, a "0" representing enabled and a "1" representing not enabled: 0000, 0100, 0010, 0001, 1000, 1100, 1110, 0111, 1011, 1101 and 1110.
Claim 11
Independent Claim
88 words
A method of selecting devices in a multi-device system, comprising: enabling all but one of the devices using a ring counter to select a different device to be not enabled each time the enabling is repeated; determining if the system operates correctly with all but one of the devices enabled; enabling a single device in the system using said ring counter if the system does not operate correctly with all but one of the devices enabled; and determining if the system operates correctly with a single device enabled.
Claim 12
Independent Claim
88 words
A method of selecting devices in a multi-device system, comprising: enabling all but one of the devices using a ring counter to select a different device to be not enabled each time the enabling is repeated; determining if the system operates correctly with all but one of the devices enabled; enabling a single device in the system using said ring counter if the system does not operate correctly with all but one of the devices enabled; and determining if the system operates correctly with a single device enabled.
Claim 13
Dependent Claim
52 words
The method of claim 10, further comprising: enabling all of the devices in the system; and determining if the system operates correctly with all of the devices enabled; said enabling all but one of the devices being performed only if the system does not operate correctly with all of the devices enabled.
Claim 14
Dependent Claim
45 words
The method of claim 11, wherein said enabling all but one of the devices and determining if the system operates correctly with all but one of the devices enabled are repeated, a different device being not enabled each time the enabling and determining are repeated.
Claim 15
Dependent Claim
38 words
The method of claim 12, wherein said enabling all but one of the devices and determining if the system operates correctly with all but one of the devices enabled are repeated until every device has been not enabled.
Claim 16
Dependent Claim
38 words
The method of claim 11, wherein said enabling a single device and determining if the system operates correctly with a single device enabled are repeated, a different device being enabled each time the enabling and determining are repeated.
Claim 17
Dependent Claim
31 words
The method of claim 14, wherein said enabling a single device and determining if the system operates correctly with a single device enabled are repeated until every device has been enabled.
Claim 18
Dependent Claim
28 words
The method of claim 15, further comprising: failing the system if the system did operate correctly with a single device enabled, and every device has been so enabled.
Claim 19
Dependent Claim
10 words
The method of claim 10, wherein the devices are processors.
Claim 20
Dependent Claim
13 words
The method of claim 17, wherein multi-device system is a four-processor computer system.
Claim 21
Dependent Claim
32 words
The method of claim 10, wherein said enabling a single device is repeated using said ring counter to select a different device to be so enabled each time the enabling is repeated.
Claim 22
Dependent Claim
20 words
The method of claim 10, wherein determining comprises: determining if the system operates correctly within a predetermined period of time.
Claim 23
Independent Claim
107 words
An apparatus that selects devices in a multi-device system, comprising: means for enabling all but one of the devices using a ring counter to select a different device to be not enabled each time the enabling is repeated; means for determining if the system operates correctly with all but one of the devices enabled; means for enabling a single device in the system using said ring counter if the system does not operate correctly with all of the devices enabled and does not operate correctly with all but one of the devices enabled; and means for determining if the system operates correctly with a single device enabled.
Claim 24
Independent Claim
107 words
An apparatus that selects devices in a multi-device system, comprising: means for enabling all but one of the devices using a ring counter to select a different device to be not enabled each time the enabling is repeated; means for determining if the system operates correctly with all but one of the devices enabled; means for enabling a single device in the system using said ring counter if the system does not operate correctly with all of the devices enabled and does not operate correctly with all but one of the devices enabled; and means for determining if the system operates correctly with a single device enabled.
Claim 25
Dependent Claim
83 words
A computer system, comprising: a plurality of processors; a system status determination unit accepting a start timer signal and a system operational signal and producing a system fail signal; and a ring counter accepting the system fail signal, said ring counter producing a plurality of processor control signals, each of said processor control signals being coupled to one of said plurality of processors, said ring counter comprising an n-bit register having said system fail signal coupled to said n-bit register's clock input signal.
Claim 26
Dependent Claim
83 words
A computer system, comprising: a plurality of processors; a system status determination unit accepting a start timer signal and a system operational signal and producing a system fail signal; and a ring counter accepting the system fail signal, said ring counter producing a plurality of processor control signals, each of said processor control signals being coupled to one of said plurality of processors, said ring counter comprising an n-bit register having said system fail signal coupled to said n-bit register's clock input signal.
References Cited (Backward Citations)
US4118688A
Cited
US4718002A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-19 | 2004-03-20 | 2004-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-19 | 2008-03-20 | 2008-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-19 | 2012-03-20 | 2012-09-19 | $7700.00 | Window Closed / Lapsed |