US6122690A
Expired / Lapsed
US
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On-chip bus architecture that is both processor independent and scalable
Assignee: Mentor Graphics Corp
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Filing: 1998-04-17
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Granted: 2000-09-19
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Expires: 2018-04-17
Abstract
Abstract A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus interface for either a bus master functional block or a slave functional block. Each bus interface includes a state machine that has at least two operational modes including a fast operational mode having two states and a normal operational mode having at least four states. A bus interface coupled to a bus master functional block implements an operational mode and a bus interface coupled to a slave functional block operates in a complementary operational mode. Each bus interface is also equipped to facilitate scaling of the address and/or data width on the bus. Various embodiments of the bus interfaces are also equipped to support multiple bus masters, broadcast writes, burst mode transfers, and/or tri-states on the bus.
Inventors
- 👤 Gianni Michele Nannetti
- 👤 Tirumal Rao Parvataneni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:58
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
106 words
An integrated circuit comprising a bus, a first bus master function block coupled to the bus, and a slave function block also coupled to the bus, the first bus master function block having a bus master interface including a state machine that conducts a bus transaction between the first bus master function block and the bus slave function block in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the at least four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
Claim 2
Dependent Claim
106 words
An integrated circuit comprising a bus, a first bus master function block coupled to the bus, and a slave function block also coupled to the bus, the first bus master function block having a bus master interface including a state machine that conducts a bus transaction between the first bus master function block and the bus slave function block in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the at least four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
Claim 3
Dependent Claim
51 words
The integrated circuit of claim 1, wherein the at least four state normal mode of operation comprises an idle state, a wait/readiness determination state, a ready state and an end of cycle state, and the two state fast mode of operation consists the idle state and the end of cycle state.
Claim 4
Dependent Claim
51 words
The integrated circuit of claim 2, wherein the at least four state normal mode of operation further comprises one or more of a slave waiting on read (SWRD) state, a master waiting on read (MWRD) state, a master waiting on write (MWWR) state and a slave waiting on write (SWWR) state.
Claim 5
Dependent Claim
49 words
The integrated circuit of claim 2, wherein the state machine includes transition logic for transitioning the bus master interface from the idle state to the wait/readiness determination state if a mode signal denotes the at least four state normal mode of operation, otherwise, to the end of cycle state.
Claim 6
Dependent Claim
35 words
The integrated circuit of claim 4, wherein the state machine further includes transition logic for automatically transitioning the bus master interface from the end of cycle state to the idle state after one clock cycle.
Claim 7
Dependent Claim
49 words
The integrated circuit of claim 4, wherein the state machine further includes transition logic for transitioning the bus master interface from the wait/readiness determination state to a slave waiting on read (SWRD) state if the slave function block is not ready and the bus transaction is a read operation.
Claim 8
Dependent Claim
50 words
The integrated circuit of claim 4, wherein the state machine further includes transition logic for transitioning the bus master interface from the wait/readiness determination state to a master waiting on write (MWWR) state if the first master function block is not ready and the bus transaction is a write operation.
Claim 9
Dependent Claim
49 words
The integrated circuit of claim 4, wherein the state machine further includes transition logic for transitioning the bus master interface from the wait/readiness determination state to a slave waiting on write (SWWR) state if the slave function block is not ready and the bus transaction is a write operation.
Claim 10
Dependent Claim
50 words
The integrated circuit of claim 4, wherein the state machine further includes transition logic for transitioning the bus master interface from the wait/readiness determination state to a master waiting on read (MWRD) state if the first master function block is not ready and the bus transaction is a read operation.
Claim 11
Dependent Claim
69 words
The integrated circuit of claim 4, wherein the state machine further includes transition logic for transitioning the bus master interface from either the wait/readiness determination state, a slave waiting on read (SWRD) state, a master waiting on write (MWWR) state, a slave waiting on write (SWWR) state, or master waiting on read (MWRD) state to the ready state if either no waiting is required or required waiting has occurred.
Claim 12
Dependent Claim
53 words
The integrated circuit of claim 1, wherein the integrated circuit further includes a second bus master function block also coupled to the bus and having a like bus master interface, and an arbitration unit also coupled to the bus for arbitrating access to the bus between the first and second master function block.
Claim 13
Dependent Claim
33 words
The integrated circuit of claim 1, wherein the first bus master function block is a microprocessor personality block, and the integrated circuit further includes a microprocessor coupled to the first master function block.
Claim 14
Dependent Claim
23 words
The integrated circuit of claim 1, wherein the bus master interface is further equipped to burst transfer data to the slave function block.
Claim 15
Dependent Claim
104 words
An integrated circuit comprising a bus, a first bus master function block coupled to the bus, and a bus slave function block also coupled to the bus, the bus slave function block having a bus slave interface including a state machine that conducts a bus transaction between the first bus master function block and the bus slave function block in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
Claim 16
Dependent Claim
104 words
An integrated circuit comprising a bus, a first bus master function block coupled to the bus, and a bus slave function block also coupled to the bus, the bus slave function block having a bus slave interface including a state machine that conducts a bus transaction between the first bus master function block and the bus slave function block in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
Claim 17
Dependent Claim
51 words
The integrated circuit of claim 14, wherein the at least four state normal mode of operation comprises an idle state, a wait/readiness determination state, a ready state and an end of cycle state, and the two state fast mode of operation consists the idle state and the end of cycle state.
Claim 18
Dependent Claim
51 words
The integrated circuit of claim 15, wherein the at least four state normal mode of operation further comprises one or more of a slave waiting on read (SWRD) state, a master waiting on read (MWRD) state, a master waiting on write (MWWR) state and a slave waiting on write (SWWR) state.
Claim 19
Dependent Claim
49 words
The integrated circuit of claim 15, wherein the state machine includes transition logic for transitioning the bus slave interface from the idle state to the wait/readiness determination state if a mode signal denotes the at least four state normal mode of operation, otherwise, to the end of cycle state.
Claim 20
Dependent Claim
35 words
The integrated circuit of claim 17, wherein the state machine further includes transition logic for automatically transitioning the bus slave interface from the end of cycle state to the idle state after one clock cycle.
Claim 21
Dependent Claim
49 words
The integrated circuit of claim 17, wherein the state machine further includes transition logic for transitioning the bus slave interface from the wait/readiness determination state to a slave waiting on read (SWRD) state if the slave function block is not ready and the bus transaction is a read operation.
Claim 22
Dependent Claim
50 words
The integrated circuit of claim 17, wherein the state machine further includes transition logic for transitioning the bus slave interface from the wait/readiness determination state to a master waiting on write (MWWR) state if the first master function block is not ready and the bus transaction is a write operation.
Claim 23
Dependent Claim
49 words
The integrated circuit of claim 17, wherein the state machine further includes transition logic for transitioning the bus slave interface from the wait/readiness determination state to a slave waiting on write (SWWR) state if the slave function block is not ready and the bus transaction is a write operation.
Claim 24
Dependent Claim
50 words
The integrated circuit of claim 17, wherein the state machine further includes transition logic for transitioning the bus master interface from the wait/readiness determination state to a master waiting on read (MWRD) state if the first master function block is not ready and the bus transaction is a read operation.
Claim 25
Dependent Claim
69 words
The integrated circuit of claim 17, wherein the state machine further includes transition logic for transitioning the bus slave interface from either the wait/readiness determination state, a slave waiting on read (SWRD) state, a master waiting on write (MWWR) state, a slave waiting on write (SWWR) state, or master waiting on read (MWRD) state to the ready state if either no waiting is required or required waiting has occurred.
Claim 26
Dependent Claim
46 words
The integrated circuit of claim 14, wherein the integrated circuit further includes a second bus master function block also coupled to the bus, and an arbitration unit also coupled to the bus for arbitrating access to the bus between the first and second master function blocks.
Claim 27
Dependent Claim
33 words
The integrated circuit of claim 14, wherein the first bus master function block is a microprocessor personality block, and the integrated circuit further includes a microprocessor coupled to the first master function block.
Claim 28
Dependent Claim
25 words
The integrated circuit of claim 14, wherein the bus slave interface is further equipped to receive burst transferred data from the first master function block.
Claim 29
Dependent Claim
145 words
An integrated circuit comprising a bus, a bus master/slave function block coupled to the bus, and either a bus master or a bus slave function block also coupled to the bus, the bus master/slave function block having a bus master/slave interface including a state machine that conducts a bus transaction with the bus master or slave function block as a bus master if the bus master or slave function block is a bus slave function block or as a bus slave if the bus master or slave function block is a bus master function block, the bus transaction being conducted in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
Claim 30
Dependent Claim
145 words
An integrated circuit comprising a bus, a bus master/slave function block coupled to the bus, and either a bus master or a bus slave function block also coupled to the bus, the bus master/slave function block having a bus master/slave interface including a state machine that conducts a bus transaction with the bus master or slave function block as a bus master if the bus master or slave function block is a bus slave function block or as a bus slave if the bus master or slave function block is a bus master function block, the bus transaction being conducted in either a two state fast mode of operation, or an at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation.
Claim 31
Dependent Claim
51 words
The integrated circuit of claim 27, wherein the at least four state normal mode of operation comprises an idle state, a wait/readiness determination state, a ready state and an end of cycle state, and the two state fast mode of operation consists the idle state and the end of cycle state.
Claim 32
Dependent Claim
51 words
The integrated circuit of claim 28, wherein the at least four state normal mode of operation further comprises one or more of a slave waiting on read (SWRD) state, a master waiting on read (MWRD) state, a master waiting on write (MWWR) state and a slave waiting on write (SWWR) state.
Claim 33
Dependent Claim
122 words
An integrated circuit comprising: a bus; a bus master function block coupled to the bus, the bus master function block having a bus master interface including a state machine that implements a two state fast mode of operation, and a at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation; and a bus slave function block coupled to the bus, the bus slave function block having a bus slave interface including a state machine that implements in a complementary manner the two state fast mode of bus operation, and the at least four state normal mode of operation.
Claim 34
Dependent Claim
122 words
An integrated circuit comprising: a bus; a bus master function block coupled to the bus, the bus master function block having a bus master interface including a state machine that implements a two state fast mode of operation, and a at least four state normal mode of operation, wherein the four states of the at least four state normal mode of operation includes the two states of the two state fast mode of operation; and a bus slave function block coupled to the bus, the bus slave function block having a bus slave interface including a state machine that implements in a complementary manner the two state fast mode of bus operation, and the at least four state normal mode of operation.
Claim 35
Dependent Claim
57 words
The integrated circuit of 30; wherein the integrated circuit further includes a bus master/slave function block coupled to the bus, the bus master/slave function block having a bus master/slave interface including a state machine that implements in a complementary manner the two state fast mode of operation, and the at least four state normal mode of operation.
Claim 36
Dependent Claim
57 words
The integrated circuit of 30; wherein the integrated circuit further includes a bus master/slave function block coupled to the bus, the bus master/slave function block having a bus master/slave interface including a state machine that implements in a complementary manner the two state fast mode of operation, and the at least four state normal mode of operation.
Claim 37
Dependent Claim
72 words
The integrated circuit of 30; wherein the integrated circuit further includes another bus master function block coupled to the bus, the other bus master function also having a bus master interface including a state machine that implements the two state fast mode of bus operation, and the at least four state normal mode of operation; and an arbiter coupled to the bus for arbitrating bus accesses for the bus master function blocks.
Claim 38
Dependent Claim
72 words
The integrated circuit of 30; wherein the integrated circuit further includes another bus master function block coupled to the bus, the other bus master function also having a bus master interface including a state machine that implements the two state fast mode of bus operation, and the at least four state normal mode of operation; and an arbiter coupled to the bus for arbitrating bus accesses for the bus master function blocks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-19 | 2004-03-20 | 2004-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-19 | 2008-03-20 | 2008-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-19 | 2012-03-20 | 2012-09-19 | $7700.00 | Window Closed / Lapsed |