Charge pumping circuit and PLL frequency synthesizer

Claim 2

A charge pumping circuit comprising: a constant current source for generating and outputting a current having a constant current value; switch means which is turned on and outputs a current determined by said constant current source when an input signal is active; a first MOS transistor for flowing the current output from said switch means; a second MOS transistor which constitutes a current mirror circuit together with said first MOS transistor, and outputs a current having a current value based on the current flowing through said first MOS transistor, as one of charge and discharge currents; and switching-off means for turning off said second MOS transistor by charging or discharging a gate when the input signal is inactive.

Claim 3

A circuit according to claim 1, wherein said switching-off means comprises: a constant current element for generating a current having a constant current value on the basis of the current from said constant current source; and a switching element which is turned on and outputs the current generated by said constant current element to a gate of said second MOS transistor when the input signal becomes inactive.

Claim 4

A circuit according to claim 2, wherein said constant current element and said switching element are respectively constituted by third and fourth MOS transistors.

Claim 5

A circuit according to claim 1, wherein said switching-off means comprises: a switching element which is turned on and outputs a current to a gate of said second MOS transistor when the input signal becomes inactive.

Claim 6

A circuit according to claim 4, wherein said switching element is constituted by a third MOS transistor.

Claim 7

A circuit according to claim 1, wherein said switch means comprises: a third MOS transistor for generating a current having a constant current value on the basis of the current from said constant current source; and a fourth MOS transistor which is turned on and supplies the current generated by said third MOS transistor to said first MOS transistor and said switching-off means when a phase error signal becomes inactive.

Claim 8

A circuit according to claim 6, wherein gates of said first and second MOS transistors are connected to each other, said switching-off means is connected between the gate of said first MOS transistor and a power supply, and a drain of said fourth MOS transistor is connected to the drain and gate of said first MOS transistor.

Claim 9

A PLL frequency synthesizer comprising: a phase comparator for detecting a phase difference between a comparison signal and a reference signal, when a phase of the comparison signal delays from a phase of the reference signal, outputting a phase error/up signal, and when the phase of the comparison signal advances from the phase of the reference signal, outputting a phase error/down signal; a charge pumping circuit for outputting charge and discharge currents on the basis of the phase error/up signal and the phase error/down signal from said phase comparator; a loop filter for generating a control voltage on the basis of the charge and discharge currents output from said charge pumping circuit; a voltage-controlled oscillator for outputting, as an oscillation output signal, a signal whose frequency is controlled by the control voltage from said loop filter; and a frequency divider for outputting, to said phase comparator, a comparison signal obtained by dividing a frequency of the oscillation output signal from said voltage-controlled oscillator, said charge pumping circuit having a constant current source for generating and outputting a current having a constant current value, switch means which is turned on and outputs a current determined by said constant current source when the phase error/up signal and the phase error/down signal are active, a first MOS transistor for flowing the current output from said switch means, a second MOS transistor which constitutes a current mirror circuit together with said first MOS transistor, and outputs a current having a current value based on the current flowing through said first MOS transistor, as one of charge and discharge currents, and switching-off means for turning off said second MOS transistor by charging or discharging a gate when the phase error/up signal and the phase error/down signal are inactive.

Claim 10

A PLL frequency synthesizer comprising: a phase comparator for detecting a phase difference between a comparison signal and a reference signal, when a phase of the comparison signal delays from a phase of the reference signal, outputting a phase error/up signal, and when the phase of the comparison signal advances from the phase of the reference signal, outputting a phase error/down signal; a charge pumping circuit for outputting charge and discharge currents on the basis of the phase error/up signal and the phase error/down signal from said phase comparator; a loop filter for generating a control voltage on the basis of the charge and discharge currents output from said charge pumping circuit; a voltage-controlled oscillator for outputting, as an oscillation output signal, a signal whose frequency is controlled by the control voltage from said loop filter; and a frequency divider for outputting, to said phase comparator, a comparison signal obtained by dividing a frequency of the oscillation output signal from said voltage-controlled oscillator, said charge pumping circuit having a constant current source for generating and outputting a current having a constant current value, switch means which is turned on and outputs a current determined by said constant current source when the phase error/up signal and the phase error/down signal are active, a first MOS transistor for flowing the current output from said switch means, a second MOS transistor which constitutes a current mirror circuit together with said first MOS transistor, and outputs a current having a current value based on the current flowing through said first MOS transistor, as one of charge and discharge currents, and switching-off means for turning off said second MOS transistor by charging or discharging a gate when the phase error/up signal and the phase error/down signal are inactive.

Claim 11

A synthesizer according to claim 8, wherein said switching-off means comprises: a constant current element for generating a current having a constant current value on the basis of the current from said constant current source; and a switching element which is turned on and outputs the current generated by said constant current element to a gate of said second MOS transistor when the phase error/up signal and the phase error/down signal become inactive.

Claim 12

A synthesizer according to claim 8, wherein said switching-off means comprises: a switching element which is turned on and outputs a current to a gate of said second MOS transistor when the phase error/up signal and the phase error/down signal become inactive.