Amplifier having bias circuit self-compensating for VGS process variation and IDS aging

Claim 2

An amplifier comprising a) a first power transistor, having a gate and a drain; b) a first sense transistor, having a gate and a drain; c) a first current sensing circuit having an output and coupled to measure a current flow through the drain of the first sense transistor; d) a first bias circuit for generating a first bias voltage, the first bias voltage being coupled to the gate of the first power transistor and to the gate of the first sense transistor, the first bias circuit having a control input coupled to the output of the first current sensing circuit; e) circuitry for coupling an input signal to the gate of the first power transistor; f) circuitry for coupling an output signal from the drain of the first power transistor and for coupling power to the first power transistor; and g) circuitry for coupling power to the first sense transistor; h) wherein the first bias circuit is controlled by the output of the first current sensing circuit so as to maintain a constant current in the first sense transistor, and thereby also maintaining a substantially constant quiescent current in the first power transistor.

Claim 3

An amplifier according to claim 1, wherein the first power transistor and the first sense transistor are of the LDMOS type.

Claim 4

An amplifier according to claim 2, wherein the first power transistor and first sense transistor are fabricated on the same die.

Claim 5

An amplifier according to claim 1, further comprising: i) a second power transistor, having a gate and a drain; j) circuitry for coupling the input signal to the gate of the second power transistor, such that an AC component of a signal at the gate of the first power transistor is approximately 180 degrees out of phase with an AC component of a signal at the gate of the second power transistor; k) circuitry for coupling the output signal from the drain of the second power transistor and for coupling power to the second power transistor; and l) circuitry for coupling the bias voltage to the gate of the second power transistor.

Claim 6

An amplifier according to claim 4, wherein the first power transistor, the second power transistor, and the first sense transistor, are fabricated on the same die.

Claim 7

An amplifier according to claim 4, wherein the first bias voltage is such that the first power transistor and the second power transistor operate as class AB push-pull amplifiers.

Claim 8

A bias circuit for an RF power amplifier having an RF amplifying device, comprising a) a MOS sense transistor having a gate and a drain; b) a current sensing circuit having an output and coupled to monitor a current through the drain of the MOS sense transistor; and c) circuitry for generating a bias voltage as a function of the output of the current sensing circuit, the bias voltage being coupled to the gate of the MOS sense transistor, and wherein the bias voltage is automatically adjusted such that an increase in the current through the drain of the MOS sense transistor as monitored by the current sensing circuit causes a change in the bias voltage in a direction that will reduce the current through the drain of the MOS sense transistor.

Claim 9

A bias circuit for an RF power amplifier having an RF amplifying device, comprising a) a MOS sense transistor having a gate and a drain; b) a current sensing circuit having an output and coupled to monitor a current through the drain of the MOS sense transistor; and c) circuitry for generating a bias voltage as a function of the output of the current sensing circuit, the bias voltage being coupled to the gate of the MOS sense transistor, and wherein the bias voltage is automatically adjusted such that an increase in the current through the drain of the MOS sense transistor as monitored by the current sensing circuit causes a change in the bias voltage in a direction that will reduce the current through the drain of the MOS sense transistor.

Claim 10

The bias circuit for an RF power amplifier of claim 7, wherein the RF amplifying device is an MOS transistor.

Claim 11

The bias circuit for an RF power amplifier of claim 8 wherein the RF amplifying device and the MOS sense transistor are both of the LDMOS type.

Claim 12

The bias circuit for an RF power amplifier of claim 9 wherein the LDMOS RF amplifying device is fabricated as a ratioed matched pair with the LDMOS sense transistor.

Claim 15

An amplifier comprising: a power transistor having a gate and a drain; a sense transistor having a gate and a drain; a current sensing circuit having an output and coupled to measure a current flow through the drain of the sense transistor; a bias circuit for generating a bias voltage, the bias voltage being coupled to the gate of the power transistor and to the gate of the sense transistor, the bias circuit having a control input coupled to the output of the current sensing circuit; circuitry for coupling an input signal to the gate of the power transistor; circuitry for coupling an output signal from the drain of the power transistor and for coupling power to the power transistor; circuitry for coupling power to the sense transistor; wherein the bias circuit is controlled by the output of the current sensing circuit so as to maintain a constant current in the sense transistor, thereby also maintaining a substantially constant quiescent current in the power transistor; and wherein the bias voltage is such that the power transistor operates as a class A amplifier.

Claim 16

An amplifier comprising: a power transistor having a gate and a drain; a sense transistor having a gate and a drain; a current sensing circuit having an output and coupled to measure a current flow through the drain of the sense transistor; a bias circuit for generating a bias voltage, the bias voltage being coupled to the gate of the power transistor and to the gate of the sense transistor, the bias circuit having a control input coupled to the output of the current sensing circuit; circuitry for coupling an input signal to the gate of the power transistor; circuitry for coupling an output signal from the drain of the power transistor and for coupling power to the power transistor; circuitry for coupling power to the sense transistor; wherein the bias circuit is controlled by the output of the current sensing circuit so as to maintain a constant current in the sense transistor, thereby also maintaining a substantially constant quiescent current in the power transistor; and wherein the bias voltage is such that the power transistor operates as a class A amplifier.

Claim 17

An amplifier according to claim 1, further comprising: i) a second power transistor, having a gate and a drain; j) a second sense transistor having a gate and a drain; k) circuitry for coupling the input signal to the gate of the second power transistor, such that an AC component of a signal at the gate of the first power transistor is approximately 180-degrees out of phase with an AC component of a signal at the gate of the second power transistor; l) a second current sensing circuit having an output and coupled to measure a current flow through the drain of the second sense transistor; m) a second bias circuit for generating a second bias voltage, the second bias voltage being coupled to the gate of the second power transistor and to the gate of the second sense transistor, the second bias circuit having a control input coupled to the output of the second current sensing circuit; n) circuitry for coupling the output signal from the drain of the second power transistor and for coupling power to the second power transistor; and o) circuitry for coupling power to the second sense transistor; p) wherein the second bias circuit is controlled by the output of the second current sensing circuit so as to maintain a constant current in the second sense transistor, thereby also maintaining a substantially constant quiescent current in the second power transistor.

Claim 18

An amplifier according to claim 13, wherein the first power transistor, the second power transistor, the first sense transistor, and the second sense transistor are of the LDMOS type.

Claim 19

An amplifier according to claim 14, wherein the first bias voltage and the second bias voltage are such that the first power transistor and the second power transistor operate as a class AB push-pull amplifier.

Claim 20

An amplifier according to claim 14, wherein the first power transistor and first sense transistor are fabricated together on the same die.

Claim 21

An amplifier according to claim 16, wherein the second power transistor and second sense transistor are fabricated together on the same die.