US6100160A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Oxide etch barrier formed by nitridation
Assignee: Texas Instruments Inc
•
Filing: 1998-02-17
•
Granted: 2000-08-08
•
Expires: 2018-02-17
Abstract
Abstract A structure and method for slowing down the etch rate of CVD oxide film 230 relative to the etch rate of thermal oxide 210 to prevent excessive removal of CVD oxide 230 during the stripping of the thermal oxide 210. Nitridation has been shown to be effective at retarding the etch rate of oxides. Therefore, nitridation of the CVD oxide 230 decreases the amount of oxide loss when thermal oxide 210 is etched. Nitridation of the wafer surface can be performed either before or after the nitride 200 removal step in standard process flows. In processes that use a densified CVD oxide 230, the densification of the CVD film 230 can be performed in an ambient that incorporates nitrogen in the film to significantly decrease the etch rate of the isolation oxide 230. Due to the porosity and the increased hydrogen content of the CVD oxide 230 as compared to the hydrogen content of thermal oxide 210, the nitrogen is incorporated more rapidly in the CVD oxide 230 than in the exposed thermal oxide 210. Therefore, the etch rate of the CVD 230 relative to the thermal oxide 210 (e.g. the selectivity) can approach one or even less than one.
Inventors
- 👤 Greg A. Hames
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:24
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
68 words
A method of fabricating an integrated circuit structure, comprising the steps of: a. forming a thick field dielectric comprising silicon and oxygen; b. at least partially nitriding the surface of said thick field dielectric to provide a nitrogen-containing composition at the surface thereof; c. growing a gate oxide layer in at least some places not covered by said thick field dielectric; and d. forming transistors in said places.
Claim 2
Independent Claim
68 words
A method of fabricating an integrated circuit structure, comprising the steps of: a. forming a thick field dielectric comprising silicon and oxygen; b. at least partially nitriding the surface of said thick field dielectric to provide a nitrogen-containing composition at the surface thereof; c. growing a gate oxide layer in at least some places not covered by said thick field dielectric; and d. forming transistors in said places.
Claim 3
Dependent Claim
18 words
The method of claim 1, wherein said step of nitriding is performed by annealing in a NH3 ambient.
Claim 4
Dependent Claim
22 words
The method of claim 1, wherein said step of nitriding is at least partially performed by using a plasma activated nitrogen anneal.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein said thick field dielectric has a hydrogen content between one and ten percent atomic.
Claim 6
Independent Claim
135 words
A method of hardening a chemical vapor deposited oxide, comprising the steps of: a. providing a partially fabricated integrated circuit structure having areas of thermal silicon oxide separating adjacent areas of chemical vapor deposited silicon oxide; b. nitriding said structure to incorporate nitrogen into said areas of chemical vapor deposited silicon oxide; c. stripping said areas of thermal silicon oxide; and d. growing a gate oxide in places where said areas of thermal silicon oxide were stripped; wherein said nitriding step decreases the etch rate of said areas of chemical vapor deposited silicon oxide relative to the etch rate of said areas of thermal silicon oxide during said stripping step; whereby excessive loss of said areas of chemical vapor deposited silicon oxide is prevented during said step of stripping said areas of thermal silicon oxide.
Claim 7
Independent Claim
135 words
A method of hardening a chemical vapor deposited oxide, comprising the steps of: a. providing a partially fabricated integrated circuit structure having areas of thermal silicon oxide separating adjacent areas of chemical vapor deposited silicon oxide; b. nitriding said structure to incorporate nitrogen into said areas of chemical vapor deposited silicon oxide; c. stripping said areas of thermal silicon oxide; and d. growing a gate oxide in places where said areas of thermal silicon oxide were stripped; wherein said nitriding step decreases the etch rate of said areas of chemical vapor deposited silicon oxide relative to the etch rate of said areas of thermal silicon oxide during said stripping step; whereby excessive loss of said areas of chemical vapor deposited silicon oxide is prevented during said step of stripping said areas of thermal silicon oxide.
Claim 8
Dependent Claim
19 words
The method of claim 5, further comprising the step of densifying said areas of chemical vapor deposited silicon oxide.
Claim 9
Dependent Claim
16 words
The method of claim 5, further comprising the step of densifying said areas of silicon oxide.
Claim 10
Dependent Claim
29 words
The method of claim 7, wherein said step of densifying is performed in an inert nitrogen atmosphere at a temperature in the range of 900 to 1000 degrees C.
Claim 11
Dependent Claim
33 words
The method of claim 5, further comprising the step, after said step of stripping, growing and stripping a sacrificial layer of thermal oxide in places where said areas of thermal oxide were stripped.
Claim 12
Dependent Claim
15 words
The method of claim 5, wherein said step of stripping is performed using buffered HF.
Claim 13
Dependent Claim
22 words
The method of claim 5, wherein said chemical vapor deposited silicon oxide has a hydrogen content between one and ten percent atomic.
Claim 14
Dependent Claim
39 words
The method of claim 5, wherein the refractive index of said thermal oxide is 1.46 and the refractive index of said chemical vapor deposited silicon oxide differs from the refractive index of said thermal oxide by at least 0.01.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-08 | 2004-02-07 | 2004-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-08 | 2008-02-07 | 2008-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-08 | 2012-02-07 | 2012-08-08 | $7700.00 | Window Closed / Lapsed |