US6097638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Kioxia Corp
•
Filing: 1998-02-11
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Granted: 2000-08-01
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Expires: 2018-02-11
Abstract
Abstract An EEPROM employs, as a scheme of detecting data of a memory cell in a memory cell array, a scheme of detecting the potential of a bit line potential sense node, which depends on the relationship in amplitude between the current for charging a bit line from a current source and the discharge current flowing to a selected cell using a sense amplifier. The sense amplifier is arranged in correspondence with one bit line and includes a constant current source transistor for charging the corresponding bit line, a latch circuit for latching memory cell data read out to the bit line potential sense node, and a switch transistor for turning on/off the charge path to the bit line based on data of the latch circuit. In the verify read mode, the cell current between the Vcc node and Vss node of a cell not to be written or a completely written cell can be turned off, so verification can be performed without flowing any unnecessary current.
Inventors
- 👤 Toshihiko Himeno
- 👤 Kazushige Kanda
- 👤 Hiroshi Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:14
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26
Claims Analysis
Total Claims: 70
Claim 1
Independent Claim
239 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines, each having a memory cell transistor for storing data upon setting a threshold value within a first range or a second range, simultaneously selected and controlled to discharge or not to discharge corresponding bit lines in accordance with the threshold value, and having paths of the discharged charges commonly connected; and a plurality of sense amplifiers, arranged in correspondence with said bit lines, configured to detect memory cell data read out to one end of the corresponding ones of said bit lines, each of said sense amplifiers comprising: a current source, arranged in correspondence with each of said bit lines, configured to charge the corresponding bit line at a predetermined timing; a latch circuit configured to latch data corresponding to the range of the threshold value of said memory cell transistor, the latch circuit having a pair of complementary nodes; a bit line potential sense MOSFET connected between a first node of the pair of complementary nodes of said latch circuit and a ground node and having a gate connected to said one end of the corresponding ones of said bit lines; and a switch circuit configured to turn on/off a charge path of the corresponding bit line based on latch data of a second node of the pair of complementary nodes of said latch circuit.
Claim 2
Dependent Claim
239 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines, each having a memory cell transistor for storing data upon setting a threshold value within a first range or a second range, simultaneously selected and controlled to discharge or not to discharge corresponding bit lines in accordance with the threshold value, and having paths of the discharged charges commonly connected; and a plurality of sense amplifiers, arranged in correspondence with said bit lines, configured to detect memory cell data read out to one end of the corresponding ones of said bit lines, each of said sense amplifiers comprising: a current source, arranged in correspondence with each of said bit lines, configured to charge the corresponding bit line at a predetermined timing; a latch circuit configured to latch data corresponding to the range of the threshold value of said memory cell transistor, the latch circuit having a pair of complementary nodes; a bit line potential sense MOSFET connected between a first node of the pair of complementary nodes of said latch circuit and a ground node and having a gate connected to said one end of the corresponding ones of said bit lines; and a switch circuit configured to turn on/off a charge path of the corresponding bit line based on latch data of a second node of the pair of complementary nodes of said latch circuit.
Claim 3
Dependent Claim
29 words
The device according to claim 1, wherein said switch circuit is inserted in a charge path for said one end of the corresponding bit line of said bit line.
Claim 4
Dependent Claim
34 words
The device according to claim 1, wherein said switch circuit is inserted in a charge path between said one end of the corresponding bit line of said bit line and said nonvolatile memory cell.
Claim 5
Dependent Claim
73 words
The device according to claim 1, in which said latch circuit is reset in reading out data from said nonvolatile memory cell, and then, stores a reset state or is forcibly inverted in accordance with the data read out to said one end of the corresponding bit line, and said switch circuit is turned on in the reset state of said latch circuit and off in the inverted state of said latch circuit.
Claim 6
Dependent Claim
47 words
The device according to claim 4, wherein said switch circuit comprises a P-channel MOSFET having a gate connected to a node which is set at "L" level in the reset state of said latch circuit and "H" level in the forcibly inverted state of said latch circuit.
Claim 7
Dependent Claim
47 words
The device according to claim 4, wherein said switch circuit comprises an N-channel MOSFET having a gate connected to a node which is set at "H" level in the reset state of said latch circuit and "L" level in the forcibly inverted state of said latch circuit.
Claim 8
Dependent Claim
158 words
The device according to claim 1, wherein said bit line potential sense MOSFET comprises a bit line potential sense N-channel MOSFET, and said sense amplifier comprises: a bit line potential clamp N-channel MOSFET inserted in series with a bit line between said one end of the corresponding ones of said bit lines and said nonvolatile memory cell; a sense timing determination N-channel MOSFET connected between said bit line potential sense N-channel MOSFET and said first node of said latch circuit and turned on/off in accordance with a signal supplied to a gate for a predetermined period; and a sense amplifier reset/transfer gate N-channel MOSFET inserted between said one end of the corresponding ones of said bit lines and said second node of said pair of complementary nodes of said latch circuit, turned off in reading out data from said nonvolatile memory cell, and turned on in resetting said latch circuit and writing data in said nonvolatile memory cell.
Claim 9
Dependent Claim
30 words
The device according to claim 1, wherein said nonvolatile memory cell constitutes a NAND cell formed of a plurality of electrically erasable and programmable memory cell transistors which are series-connected.
Claim 10
Dependent Claim
187 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines, each having a memory cell transistor for storing data upon setting a threshold value within a first range or a second range, simultaneously selected and controlled to discharge or not to discharge corresponding bit lines in accordance with the threshold value, and having paths of the discharged charges commonly connected; a plurality of sense amplifiers arranged in correspondence with said bit lines configured to detect memory cell data read out to one end of the corresponding ones of said bit lines, each of said sense amplifiers comprising a current source, arranged in correspondence with each of said bit lines, configured to detect the corresponding bit line at a predetermined timing, and a latch circuit configured to latch data corresponding to the range of the threshold value of said memory cell transistor; and a control circuit configured to decrease an amplitude of a current of said current source charging said bit line in a verify mode to be smaller than that in a read mode.
Claim 11
Dependent Claim
187 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines, each having a memory cell transistor for storing data upon setting a threshold value within a first range or a second range, simultaneously selected and controlled to discharge or not to discharge corresponding bit lines in accordance with the threshold value, and having paths of the discharged charges commonly connected; a plurality of sense amplifiers arranged in correspondence with said bit lines configured to detect memory cell data read out to one end of the corresponding ones of said bit lines, each of said sense amplifiers comprising a current source, arranged in correspondence with each of said bit lines, configured to detect the corresponding bit line at a predetermined timing, and a latch circuit configured to latch data corresponding to the range of the threshold value of said memory cell transistor; and a control circuit configured to decrease an amplitude of a current of said current source charging said bit line in a verify mode to be smaller than that in a read mode.
Claim 12
Dependent Claim
31 words
The device according to claim 9, wherein said control circuit prolongs a read time of said sense amplifier in the verify mode to be longer than that in the read mode.
Claim 13
Dependent Claim
33 words
The device according to claim 9, wherein said control circuit prolongs a read time of said sense amplifier in inverse proportion to the current of said current source for charging said bit line.
Claim 14
Dependent Claim
31 words
The device according to claim 9, wherein said control circuit increases a load resistance of said bit line in the verify mode to be larger than that in the read mode.
Claim 15
Dependent Claim
28 words
The device according to claim 12, wherein said control circuit prolongs a read time of said sense amplifier in proportion to the load resistance of said bit line.
Claim 16
Dependent Claim
30 words
The device according to claim 9, wherein said nonvolatile memory cell constitutes a NAND cell formed of a plurality of electrically erasable and programmable memory cell transistors which are series-connected.
Claim 17
Dependent Claim
154 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source configured to supply a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switch transistor, connected between the current source and the one end of the bit line and having a gate connected to the second node of the latch circuit, and being turned on/off in accordance with a voltage of the second node.
Claim 18
Dependent Claim
154 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source configured to supply a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switch transistor, connected between the current source and the one end of the bit line and having a gate connected to the second node of the latch circuit, and being turned on/off in accordance with a voltage of the second node.
Claim 19
Dependent Claim
30 words
The sense amplifier according to claim 15, further comprising: a latch circuit inverting transistor connected between the first node of the latch circuit and the bit line potential sense MOSFET.
Claim 20
Dependent Claim
36 words
The sense amplifier according to claim 15, further comprising: a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 21
Dependent Claim
81 words
The sense amplifier according to claim 15, further comprising: a latch circuit inverting transistor connected to the second sense node of the latch circuit; a bit line sense transistor connected between the latch circuit inverting transistor and a ground terminal and having a gate connected to the one end of the bit line; and a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 22
Dependent Claim
70 words
The sense amplifier according to claim 15, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a relationship between a current for charging the bit line from the current source and a discharge current flowing to the memory cell and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 23
Dependent Claim
67 words
The sense amplifier according to claim 19, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a cell current after charging the bit line from the current source and then stopping charging of the bit line and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 24
Dependent Claim
151 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, supplying a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; a switch transistor, connected between the current source and the one end of the bit line and having a gate connected to the first node of the latch circuit, and being turned on/off in accordance with a voltage of the first node.
Claim 25
Dependent Claim
151 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, supplying a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; a switch transistor, connected between the current source and the one end of the bit line and having a gate connected to the first node of the latch circuit, and being turned on/off in accordance with a voltage of the first node.
Claim 26
Dependent Claim
30 words
The sense amplifier according to claim 21, further comprising: a latch circuit inverting transistor connected between the first node of the latch circuit and the bit line potential sense MOSFET.
Claim 27
Dependent Claim
36 words
The sense amplifier according to claim 21, further comprising: a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 28
Dependent Claim
81 words
The sense amplifier according to claim 21, further comprising: a latch circuit inverting transistor connected to the second sense node of the latch circuit; a bit line sense transistor connected between the latch circuit inverting transistor and a ground terminal and having a gate connected to the one end of the bit line; and a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 29
Dependent Claim
70 words
The sense amplifier according to claim 21, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a relationship between a current for charging the bit line from the current source and a discharge current flowing to the memory cell and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 30
Dependent Claim
67 words
The sense amplifier according to claim 21, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a cell current after charging the bit line from the current source and then stopping charging of the bit line and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 31
Dependent Claim
152 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, supplying a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the first node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switch transistor, connected between the memory cell and the one end of the bit line and having a gate connected to the first node of the latch circuit, and being turned on/off in accordance with a voltage of the first node.
Claim 32
Dependent Claim
152 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, supplying a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the first node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switch transistor, connected between the memory cell and the one end of the bit line and having a gate connected to the first node of the latch circuit, and being turned on/off in accordance with a voltage of the first node.
Claim 33
Dependent Claim
30 words
The sense amplifier according to claim 22, further comprising: a latch circuit inverting transistor connected between the first node of the latch circuit and the bit line potential sense MOSFET.
Claim 34
Dependent Claim
36 words
The sense amplifier according to claim 27, further comprising: a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 35
Dependent Claim
81 words
The sense amplifier according to claim 27, further comprising: a latch circuit inverting transistor connected to the second sense node of the latch circuit; a bit line sense transistor connected between the latch circuit inverting transistor and a ground terminal and having a gate connected to the one end of the bit line; and a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 36
Dependent Claim
69 words
The sense amplifier according to claim 22, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a relationship between a current for charging the bit line from the current source and discharge current flowing to the memory cell and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 37
Dependent Claim
67 words
The sense amplifier according to claim 27, wherein said sense amplifier sense a potential of the one end of the bit line in accordance with a cell current after charging the bit line from the current source and then stopping charging of the bit line and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 38
Dependent Claim
152 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, supplying a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switch transistor, connected between the memory cell and the one end of the bit line and having a gate connected to the second node of the latch circuit, and being turned on/off in accordance with a voltage of the second node.
Claim 39
Dependent Claim
152 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, supplying a current to the one end of the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switch transistor, connected between the memory cell and the one end of the bit line and having a gate connected to the second node of the latch circuit, and being turned on/off in accordance with a voltage of the second node.
Claim 40
Dependent Claim
30 words
The sense amplifier according to claim 33, further comprising: a latch circuit inverting transistor connected between the first node of the latch circuit and the bit line potential sense MOSFET.
Claim 41
Dependent Claim
36 words
The sense amplifier according to claim 33, further comprising: a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 42
Dependent Claim
81 words
The sense amplifier according to claim 33, further comprising: a latch circuit inverting transistor connected to the second sense node of the latch circuit; a bit line sense transistor connected between the latch circuit inverting transistor and a ground terminal and having a gate connected to the one end of the bit line; and a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 43
Dependent Claim
70 words
The sense amplifier according to claim 33, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a relationship between a current for charging the bit line from the current source and a discharge current flowing to the memory cell and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 44
Dependent Claim
67 words
The sense amplifier according to claim 33, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a cell current after charging the bit line from the current source and then stopping charging of the bit line and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 45
Dependent Claim
94 words
The device according to claim 9, wherein said sense amplifier comprises: a current mirror transistor having a source connected to a power source and a gate connected to a gate of the current source transistor and to a drain of the current mirror transistor; and a control transistor, connected between the current mirror transistor and a ground terminal, having a gate whose voltage is controlled to decrease an amplitude of a current of said current source for charging said bit line in a verify mode to be smaller than that in a read mode.
Claim 46
Dependent Claim
114 words
The device according to claim 9, wherein said sense amplifier comprises: a current mirror transistor having a source connected to a power source and a gate connected to a gate of the current source transistor and to a drain of the current mirror transistor; a first control transistor connected between the current mirror transistor and a ground terminal; and a second control transistor connected between the gate of the current mirror transistor and the ground terminal, the first and second control transistors, being turned on to increase an amplitude of a current of said current source for charging said bit line in a read mode to be larger than that in a verify mode.
Claim 47
Dependent Claim
154 words
The device according to claim 9, wherein said sense amplifier comprises: a first current mirror transistor having a gate connected to a gate of the current source transistor; a first switching transistor connected between the first current mirror transistor and a power source, the first switching transistor being turned on in a verify mode and a read mode; a second current mirror transistor having a gate connected to the gate of the current source transistor; a second switching transistor connected between the second current mirror transistor and the power source, the second switching transistor being turned on in the verify mode; and a control transistor, connected between the first and second current mirror transistors and a ground terminal, having a gate whose voltage is controlled to decrease an amplitude of a current of said current source for charging said bit line in a verify mode to be smaller than that in a read mode.
Claim 48
Dependent Claim
173 words
The device according to claim 9, wherein said sense amplifier comprises: a first current source transistor, connected to the bit line, for charging the bit line at a predetermined timing; a first switching transistor, connected between the first current source transistor and a power source, which is turned on in a verify mode and a read mode; a second current source transistor, connected to the bit line, for charging the bit line at a predetermined timing; a second switching transistor, connected between the first current source transistor and the power source, which is turned on in the read mode; a current mirror transistor having a source connected to the power source and a gate connected to a drain of the current mirror transistor; and a control transistor, connected between the current mirror transistor and a ground terminal, having a gate whose voltage is controlled to decrease an amplitude of a current of said current source for charging said bit line in a verify mode to be smaller than that in a read mode.
Claim 49
Dependent Claim
185 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, connected to the one end of the bit line, for charging the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switching circuit formed of first and second transistors, connected between the current source and a precharge power source, a gate of the first transistor being connected to the first node of the latch circuit, and a gate of the second transistor being connected to the second node of the latch circuit, the switching circuit turning on/off a charge path of the bit line based on latch data of said latch circuit.
Claim 50
Dependent Claim
185 words
A sense amplifier connected to a bit line of a semiconductor memory device for detecting memory cell data read out to a one end of the bit line, the sense amplifier comprising: a current source, connected to the one end of the bit line, for charging the bit line at a predetermined timing; a latch circuit having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the bit line; a bit line potential sense MOSFET connected between the first node of said latch circuit and a ground node and having a gate connected to said one end of the bit line; and a switching circuit formed of first and second transistors, connected between the current source and a precharge power source, a gate of the first transistor being connected to the first node of the latch circuit, and a gate of the second transistor being connected to the second node of the latch circuit, the switching circuit turning on/off a charge path of the bit line based on latch data of said latch circuit.
Claim 51
Dependent Claim
30 words
The sense amplifier according to claim 43, further comprising: a latch circuit inverting transistor connected between the first node of the latch circuit and the bit line potential sense MOSFET.
Claim 52
Dependent Claim
36 words
The sense amplifier according to claim 43, further comprising: a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 53
Dependent Claim
81 words
The sense amplifier according to claim 43, further comprising: a latch circuit inverting transistor connected to the second sense node of the latch circuit; a bit line sense transistor connected between the latch circuit inverting transistor and a ground terminal and having a gate connected to the one end of the bit line; and a discharge transistor, connected between the one end of the bit line and the ground terminal, for discharging charges at the one end of the bit line.
Claim 54
Dependent Claim
70 words
The sense amplifier according to claim 43, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a relationship between a current for charging the bit line from the current source and a discharge current flowing to the memory cell and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 55
Dependent Claim
67 words
The sense amplifier according to claim 43, wherein said sense amplifier senses a potential of the one end of the bit line in accordance with a cell current after charging the bit line from the current source and then stopping charging of the bit line and further comprising a read controller for resetting the sense amplifier and then performing a read operation in a normal read mode.
Claim 56
Dependent Claim
183 words
A semiconductor memory device comprising: a plurality of bit lines, each having one end; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines; a plurality of latch circuits, each arranged in correspondence with said bit lines and having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the corresponding one bit line; a plurality of current sources, each arranged in correspondence with each of said bit lines, and the current source supplying a current to the corresponding bit line for charging the corresponding bit line at a predetermined timing; a plurality of bit line potential sense MOSFETs connected between the first node of the corresponding one of said latch circuits and a ground node and having a gate connected to said one end of the corresponding bit line; and a plurality of switch circuits connected to the current sources respectively, for determining whether the corresponding current source charges the corresponding bit line or not in accordance with a voltage of the first nodes of the corresponding latch circuits.
Claim 57
Dependent Claim
183 words
A semiconductor memory device comprising: a plurality of bit lines, each having one end; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines; a plurality of latch circuits, each arranged in correspondence with said bit lines and having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the corresponding one bit line; a plurality of current sources, each arranged in correspondence with each of said bit lines, and the current source supplying a current to the corresponding bit line for charging the corresponding bit line at a predetermined timing; a plurality of bit line potential sense MOSFETs connected between the first node of the corresponding one of said latch circuits and a ground node and having a gate connected to said one end of the corresponding bit line; and a plurality of switch circuits connected to the current sources respectively, for determining whether the corresponding current source charges the corresponding bit line or not in accordance with a voltage of the first nodes of the corresponding latch circuits.
Claim 58
Dependent Claim
28 words
The device according to claim 49, wherein each of said switch circuit is connected between the corresponding current source and the one end of the corresponding bit line.
Claim 59
Dependent Claim
23 words
The device according to claim 49, wherein each of said switch circuits is connected to the one end of the corresponding bit line.
Claim 60
Dependent Claim
77 words
The device according to claim 49, wherein each of said latch circuits is reset in reading out data from said nonvolatile memory cell, and then, stores a reset state or is forcibly inverted in accordance with the data read out to the one end of the corresponding bit line, and each of said switch circuits is turned on in the reset state of said corresponding latch circuit and off in the inverted state of said latch circuit.
Claim 61
Dependent Claim
49 words
The device according to claim 52, wherein each of said switch circuits comprises a P-channel MOSFET having a gate connected to a node which is set at "L" level in the reset state of said latch circuit and "H" level in the forcibly inverted state of said latch circuit.
Claim 62
Dependent Claim
49 words
The device according to claim 52, wherein each of said switch circuits comprises an N-channel MOSFET having a gate connected to a node which is set at "H" level in the reset state of said latch circuit and "L" level in the forcibly inverted state of said latch circuit.
Claim 63
Dependent Claim
30 words
The device according to claim 49, wherein said nonvolatile memory cell constitutes a NAND cell formed of a plurality of electrically erasable and programmable memory cell transistors which are series-connected.
Claim 64
Dependent Claim
166 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines; a plurality of latch circuits, each arranged in correspondence with said bit lines and having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the corresponding one bit line; a plurality of current sources, each arranged in correspondence with each of said bit lines and supplying a current to the corresponding bit line at a predetermined timing; a plurality of bit line potential sense MOSFETs connected between the first node of the corresponding one of said latch circuits and a ground node and having a gate connected to said one end of the corresponding bit line; and a control circuit for decreasing a amplitude of the current of said current sources to be supplied to the corresponding bit line in a verify mode to be smaller than that in a read mode.
Claim 65
Dependent Claim
166 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of nonvolatile memory cells arranged in correspondence with said bit lines; a plurality of latch circuits, each arranged in correspondence with said bit lines and having first and second nodes, the second node receiving a voltage in accordance with a voltage of the one end of the corresponding one bit line; a plurality of current sources, each arranged in correspondence with each of said bit lines and supplying a current to the corresponding bit line at a predetermined timing; a plurality of bit line potential sense MOSFETs connected between the first node of the corresponding one of said latch circuits and a ground node and having a gate connected to said one end of the corresponding bit line; and a control circuit for decreasing a amplitude of the current of said current sources to be supplied to the corresponding bit line in a verify mode to be smaller than that in a read mode.
Claim 66
Dependent Claim
31 words
The device according to claim 56, wherein said control circuit prolongs a read time of said latch circuits in the verify mode to be longer than that in the read mode.
Claim 67
Dependent Claim
33 words
The device according to claim 56, wherein said control circuit prolongs a read time of said latch circuits in inverse proportion to the current of said current sources for charging said bit lines.
Claim 68
Dependent Claim
31 words
The device according to claim 56, wherein said control circuit increases a load resistance of said bit lines in the verify mode to be larger than that in the read mode.
Claim 69
Dependent Claim
28 words
The device according to claim 59, wherein said control circuit prolongs a read time of said latch circuits in proportion to the load resistance of said bit lines.
Claim 70
Dependent Claim
31 words
The device according to claim 56, wherein said nonvolatile memory cell constitutes a NAND cell formed of a plurality of electrically erasable and programmable memory cell transistors which are series connected.
References Cited (Backward Citations)
US5357462A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-01 | 2004-01-31 | 2004-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-01 | 2008-01-31 | 2008-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-01 | 2012-01-31 | 2012-08-01 | $7700.00 | Window Closed / Lapsed |