US6091280A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS image sensor based on four transistor photocell
Assignee: Texas Instruments Inc
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Filing: 1998-04-21
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Granted: 2000-07-18
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Expires: 2018-04-21
Abstract
Abstract An image sensing cell includes: a light sensing device 18; a first transistor 10 having a first node coupled to the light sensing device 18; a second transistor 12 having a first node coupled to a second node of the first transistor 10; a third transistor 14 having a control node coupled to the light sensing device 18; and a fourth transistor 16 having a first node coupled to a first node of the third transistor.
Inventors
- 👤 Jaroslav Hynecek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:35
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/80; H10F39/803; H04; H04N; H04N25/00; H04N25/60; H04N25/616; H04N25/70; H04N25/76; H04N25/77; H04N25/78
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
96 words
An image sensing cell comprising: a light sensing device; a first transistor having a first node coupled to the light sensing device; a second transistor having a first node coupled to a second node of the first transistor; a third transistor having a control node coupled to the light sensing device; a fourth transistor having a first node coupled to a first node of the third transistor; and a column sense line coupled to a second node of the fourth transistor and the column sense line is coupled to a control node of the second transistor.
Claim 2
Dependent Claim
96 words
An image sensing cell comprising: a light sensing device; a first transistor having a first node coupled to the light sensing device; a second transistor having a first node coupled to a second node of the first transistor; a third transistor having a control node coupled to the light sensing device; a fourth transistor having a first node coupled to a first node of the third transistor; and a column sense line coupled to a second node of the fourth transistor and the column sense line is coupled to a control node of the second transistor.
Claim 3
Dependent Claim
16 words
The device of claim 1 wherein the first, second, third, and fourth transistors are MOS transistors.
Claim 4
Dependent Claim
16 words
The device of claim 1 wherein the first, second, third, and fourth transistors are NMOS transistors.
Claim 5
Dependent Claim
19 words
The device of claim 1 wherein the first and second transistors are formed as a dual gate transistor structure.
Claim 6
Dependent Claim
19 words
The device of claim 1 wherein the third and fourth transistors are formed as a dual gate transistor structure.
Claim 7
Dependent Claim
16 words
The device of claim 1 further comprising a reset switch coupled to the column sense line.
Claim 8
Dependent Claim
28 words
The device of claim 1 wherein a control node of the first transistor and a control node of the fourth transistor are coupled to a row address node.
Claim 9
Dependent Claim
27 words
The device of claim 1 wherein a second node of the second transistor and a second node of the third transistor are coupled to a bias node.
Claim 10
Dependent Claim
13 words
The device of claim 1 wherein the light sensing device is a photodiode.
Claim 11
Dependent Claim
91 words
An image sensing cell comprising: a light sensing device; a first transistor having a first node coupled to the light sensing device; a second transistor having a first node coupled to a second node of the first transistor; a third transistor having a control node coupled to the light sensing device; and a fourth transistor having a first node coupled to a first node of the third transistor, wherein a control node of the first transistor and a control node of the fourth transistor are coupled to a row address node.
Claim 12
Dependent Claim
91 words
An image sensing cell comprising: a light sensing device; a first transistor having a first node coupled to the light sensing device; a second transistor having a first node coupled to a second node of the first transistor; a third transistor having a control node coupled to the light sensing device; and a fourth transistor having a first node coupled to a first node of the third transistor, wherein a control node of the first transistor and a control node of the fourth transistor are coupled to a row address node.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-18 | 2008-01-17 | 2008-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-18 | 2012-01-17 | 2012-07-18 | $7700.00 | Window Closed / Lapsed |