US6087904A
Expired / Lapsed
US
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Amplitude modulation and amplitude shift keying circuit
Assignee: Oki Electric Industry Co Ltd
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Filing: 1998-09-30
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Granted: 2000-07-11
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Expires: 2018-09-30
Abstract
Abstract The present invention provides a modulation circuit that has excellent modulation characteristics and can be designed as an MMIC. Consequently, this modulation circuit is such that the modulating wave input means is composed of a capacitor 21 and an inductor 22, the carrier input means is composed of a capacitor 23 and a resistance element 24, the self-bias means is composed of a resistance element 26 and a capacitor 27, the carrier selection means is composed of an inductor 22 and a capacitor 28, and the modulated wave output means is composed of a capacitor 28.
Inventors
- 👤 Zhongmin Wen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:47
CPC Classifications
H; H03; H03C; H03C1/00; H03C1/36
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
141 words
A modulation circuit, comprising: carrier input means for directly inputting a carrier to a carrier input terminal; a transistor for inputting the carrier inputted by the carrier input means to a control terminal, amplifying the carrier, and outputting the result to a first terminal; modulating wave input means for directly inputting a modulating wave to a modulating wave input terminal and feeding the modulating wave to said first terminal of said transistor while preventing said carrier from being transmitted; self-bias means for setting the bias potential of said transistor; carrier selection means having a parallel resonant circuit for selectively extracting said amplified carrier from said first terminal of said transistor; and modulated wave output means for extracting the modulated wave from said carrier selectively extracted by the carrier selection means, and outputting the result directly to a modulated wave output terminal.
Claim 2
Dependent Claim
141 words
A modulation circuit, comprising: carrier input means for directly inputting a carrier to a carrier input terminal; a transistor for inputting the carrier inputted by the carrier input means to a control terminal, amplifying the carrier, and outputting the result to a first terminal; modulating wave input means for directly inputting a modulating wave to a modulating wave input terminal and feeding the modulating wave to said first terminal of said transistor while preventing said carrier from being transmitted; self-bias means for setting the bias potential of said transistor; carrier selection means having a parallel resonant circuit for selectively extracting said amplified carrier from said first terminal of said transistor; and modulated wave output means for extracting the modulated wave from said carrier selectively extracted by the carrier selection means, and outputting the result directly to a modulated wave output terminal.
Claim 3
Dependent Claim
29 words
The modulation circuit according to claim 1, wherein said transistor is a field-effect transistor, said control terminal is a gate terminal, and said first terminal is a drain terminal.
Claim 4
Dependent Claim
67 words
The modulation circuit according claim 2, wherein said carrier input means comprises a capacitor, one end of which is connected to said carrier input terminal, and the other end of which is connected to said gate terminal of said field-effect transistor; and a resistance element, one end of which is connected to said gate terminal of said field-effect transistor, and the other end of which is grounded.
Claim 5
Dependent Claim
66 words
The modulation circuit according claim 2, wherein said modulating wave input means comprises a capacitor, one end of which is connected to said modulating wave input terminal, and the other end of which is grounded; and an inductor, one end of which is connected to said modulating wave input terminal, and the other end of which is connected to said drain terminal of said field-effect transistor.
Claim 6
Dependent Claim
36 words
The modulation circuit according claim 2, wherein said self-bias means comprises a resistance element one end of which is connected to the source terminal of said field-effect transistor, and the other end of which is grounded.
Claim 7
Dependent Claim
33 words
The modulation circuit according to claim 2, comprising a bypass capacitor one end of which is connected to the source terminal of said field-effect transistor, and the other end of which is grounded.
Claim 8
Dependent Claim
68 words
The modulation circuit according to claim 2, wherein said carrier selection means comprises an inductor, one end of which is connected to said modulating wave input terminal, and the other end of which is connected to said drain terminal of said field-effect transistor; and a capacitor, one end of which is connected to said drain terminal of said field-effect transistor, and the other end of which is grounded.
Claim 9
Dependent Claim
44 words
The modulation circuit according to claim 2, wherein said modulated wave output means comprises a capacitor one end of which is connected to said drain terminal of said field-effect transistor, and the other end of which is connected to said modulated wave output terminal.
Claim 10
Dependent Claim
29 words
The modulation circuit according to claim 1, wherein said transistor is a bipolar transistor, said control terminal is a base terminal, and said first terminal is a collector terminal.
Claim 11
Dependent Claim
68 words
The modulation circuit according to claim 9, wherein said carrier input means comprises a capacitor, one end of which is connected to said carrier input terminal, and the other end of which is connected to said base terminal of said bipolar transistor; and a resistance element, one end of which is connected to said base terminal of said bipolar transistor, and the other end of which is grounded.
Claim 12
Dependent Claim
67 words
The modulation circuit according to claim 9, wherein said modulating wave input means comprises a capacitor, one end of which is connected to said modulating wave input terminal, and the other end of which is grounded; and an inductor, one end of which is connected to said modulating wave input terminal, and the other end of which is connected to said collector terminal of said bipolar transistor.
Claim 13
Dependent Claim
97 words
The modulation circuit according to claim 9, wherein said self-bias means comprises a first resistance element, one end of which is connected to said modulating wave input terminal, and the other end of which is connected to said base terminal of said bipolar transistor; a second resistance element, one end of which is connected to said base terminal of said bipolar transistor, and the other end of which is grounded; and a third resistance element, one end of which is connected to the emitter terminal of said bipolar transistor, and the other end of which is grounded.
Claim 14
Dependent Claim
33 words
The modulation circuit according to claim 9, comprising a bypass capacitor one end of which is connected to the emitter terminal of said bipolar transistor, and the other end of which is grounded.
Claim 15
Dependent Claim
68 words
The modulation circuit according to claim 9, wherein said carrier selection means comprises an inductor, one end of which is connected to said modulating wave input terminal, and the other end of which is connected to said collector terminal of said bipolar transistor; and a capacitor, one end of which is connected to said collector terminal of said bipolar transistor, and the other end of which is grounded.
Claim 16
Dependent Claim
44 words
The modulation circuit according to claim 9, wherein said modulated wave output means comprises a capacitor one end of which is connected to said collector terminal of said bipolar transistor, and the other end of which is connected to said modulated wave output terminal.
Claim 17
Dependent Claim
14 words
The modulation circuit according to claim 1, composed of a monolithic microwave integrated circuit.
References Cited (Backward Citations)
US3484723A
Cited
US5680078A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |