US6075829A
Expired / Lapsed
US
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Digital broadcast receiver
Assignee: Panasonic Holdings Corp
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Filing: 1997-05-30
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Granted: 2000-06-13
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Expires: 2017-05-30
Abstract
Abstract A digital broadcast receiver for receiving a digital modulation signal of the present invention includes channel selection means inputting a digital modulation signal of a radio frequency band and frequency converting a desired digital modulation signal into a designated intermediate frequency signal; oscillation means for generating a local oscillation signal used for frequency conversion at the channel selection means; oscillation frequency control means for controlling a frequency of the local oscillation signal at the oscillation means; phase noise characteristic control means for improving a phase noise characteristic of the local oscillation signal generated at the oscillation means; filter means for extracting the intermediate frequency signal selected at channel selection means; orthogonal detection means for orthogonally detecting the intermediate frequency signal extracted at the filter means; A/D converter means for converting the analog output of the orthogonal detection means into a digital signal; and digital demodulation means for digitally demodulating the output of the A/D converter means; and makes a high performance digital reception possible which can improve an AFC function by the channel selection means and can improve a bit error rate at the same time.
Inventors
- 👤 Yoshikazu Hayashi
- 👤 Noriaki Omoto
- 👤 Takaaki Konishi
- 👤 Hiroshi Azakami
- 👤 Takashi Hasegawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:57
CPC Classifications
H; H04; H04B; H04B7/00; H04B7/14; H04B7/15; H04H; H04H40/00; H04H40/18; H03; H03B; H03B5/00; H03B5/08; H03B5/12; H03B5/1203; H03B5/1231; H03B5/1237; H03B5/124; H03B5/1243; H03D; H03D3/00; H03D3/007; H03J; H03J1/00; H03J1/0008; H03J1/0041; H03J1/005; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H04L; H04L1/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
209 words
A digital receiver comprising: a PLL for generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a mixer for converting a QPSK (quaternary phase-shift keying) modulated signal into a first intermediate frequency signal based on the local oscillation signal; a bandpass filter for extracting a second intermediate frequency signal from the first intermediate frequency signal; orthogonal detector for detecting an in-phase component I and a quadrature component Q of the second intermediate frequency signal and for continuously compensating a frequency drift of the second intermediate frequency signal; an A/D converter for converting the in-phase component signal I and the quadrature component signal Q of the second intermediate frequency signal to a digital in-phase component signal and a digital quadrature component signal; QPSK demodulator for digitally demodulating the digital in-phase component signal and the digital quadrature component signal and for producing an encoded and multiplexed signal; error correction means for correcting transmission errors of the encoded and multiplexed signal; and a demultiplexer for demultiplexing the output of said error correction means and for producing a system clock signal, wherein the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the system clock signal produced by said demultiplexer.
Claim 2
Dependent Claim
209 words
A digital receiver comprising: a PLL for generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a mixer for converting a QPSK (quaternary phase-shift keying) modulated signal into a first intermediate frequency signal based on the local oscillation signal; a bandpass filter for extracting a second intermediate frequency signal from the first intermediate frequency signal; orthogonal detector for detecting an in-phase component I and a quadrature component Q of the second intermediate frequency signal and for continuously compensating a frequency drift of the second intermediate frequency signal; an A/D converter for converting the in-phase component signal I and the quadrature component signal Q of the second intermediate frequency signal to a digital in-phase component signal and a digital quadrature component signal; QPSK demodulator for digitally demodulating the digital in-phase component signal and the digital quadrature component signal and for producing an encoded and multiplexed signal; error correction means for correcting transmission errors of the encoded and multiplexed signal; and a demultiplexer for demultiplexing the output of said error correction means and for producing a system clock signal, wherein the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the system clock signal produced by said demultiplexer.
Claim 3
Dependent Claim
235 words
A digital receiver comprising: a PLL for generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a mixer for converting a QPSK (quaternary phase-shift keying) modulated signal into a first intermediate frequency signal based on the local oscillation signal; a bandpass filter for extracting a second intermediate frequency signal from the first intermediate frequency signal; orthogonal detector for detecting an in-phase component I and a quadrature component Q of the second intermediate frequency signal and for continuously compensating a frequency drift of the second intermediate frequency signal; an A/D converter for converting the in-phase component signal I and the quadrature component signal Q of the second intermediate frequency signal to a digital in-phase component signal and a digital quadrature component signal; QPSK demodulator for digitally demodulating the digital in-phase component signal and the digital quadrature component signal and for producing an encoded and multiplexed signal; error correction means for correcting transmission errors of the encoded and multiplexed signal; a demultiplexer for demultiplexing the output of said error correction means and for generating a synchronization signal; a microcomputer for controlling the PLL based on the synchronization signal; and a control bus for relaying a control signal from the microcomputer to the PLL, wherein the microcomputer resets the PLL by relaying the control signal via the control bus when the demultiplexer indicates a loss of synchronization via the synchronization signal.
Claim 4
Dependent Claim
235 words
A digital receiver comprising: a PLL for generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a mixer for converting a QPSK (quaternary phase-shift keying) modulated signal into a first intermediate frequency signal based on the local oscillation signal; a bandpass filter for extracting a second intermediate frequency signal from the first intermediate frequency signal; orthogonal detector for detecting an in-phase component I and a quadrature component Q of the second intermediate frequency signal and for continuously compensating a frequency drift of the second intermediate frequency signal; an A/D converter for converting the in-phase component signal I and the quadrature component signal Q of the second intermediate frequency signal to a digital in-phase component signal and a digital quadrature component signal; QPSK demodulator for digitally demodulating the digital in-phase component signal and the digital quadrature component signal and for producing an encoded and multiplexed signal; error correction means for correcting transmission errors of the encoded and multiplexed signal; a demultiplexer for demultiplexing the output of said error correction means and for generating a synchronization signal; a microcomputer for controlling the PLL based on the synchronization signal; and a control bus for relaying a control signal from the microcomputer to the PLL, wherein the microcomputer resets the PLL by relaying the control signal via the control bus when the demultiplexer indicates a loss of synchronization via the synchronization signal.
Claim 5
Dependent Claim
39 words
A digital receiver as recited in claim 2, wherein the QPSK demodulator recovers a clock signal and the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the frequency of the clock signal.
Claim 6
Dependent Claim
41 words
A digital receiver as recited in claim 2, wherein wherein the demultiplexer produces a system clock signal and the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the frequency of the system clock signal.
Claim 7
Dependent Claim
245 words
A digital receiver comprising: a PLL for generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a mixer for converting a QPSK (quaternary phase-shift keying) modulated signal into a first intermediate frequency signal based on the local oscillation signal; a bandpass filter for extracting a second intermediate frequency signal from the first intermediate frequency signal; orthogonal detector for detecting an in-phase component I and a quadrature component Q of the second intermediate frequency signal and for continuously compensating a frequency drift of the second intermediate frequency signal; an A/D converter for converting the in-phase component signal I and the quadrature component signal Q of the second intermediate frequency signal to a digital in-phase component signal and a digital quadrature component signal; QPSK demodulator for digitally demodulating the digital in-phase component signal and the digital quadrature component signal and for producing an encoded and multiplexed signal; error correction means for correcting transmission errors of the encoded and multiplexed signal, for outputting a corrected multiplexed signal, and for generating a synchronization signal; a demultiplexer for demultiplexing the corrected multiplexed signal of said error correction means; a microcomputer for controlling the PLL based on the synchronization signal; and a control bus for relaying a control signal from the microcomputer to the PLL, wherein the microcomputer resets the PLL by relaying the control signal via the control bus when the error correction means indicates a loss of synchronization via the synchronization signal.
Claim 8
Dependent Claim
245 words
A digital receiver comprising: a PLL for generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a mixer for converting a QPSK (quaternary phase-shift keying) modulated signal into a first intermediate frequency signal based on the local oscillation signal; a bandpass filter for extracting a second intermediate frequency signal from the first intermediate frequency signal; orthogonal detector for detecting an in-phase component I and a quadrature component Q of the second intermediate frequency signal and for continuously compensating a frequency drift of the second intermediate frequency signal; an A/D converter for converting the in-phase component signal I and the quadrature component signal Q of the second intermediate frequency signal to a digital in-phase component signal and a digital quadrature component signal; QPSK demodulator for digitally demodulating the digital in-phase component signal and the digital quadrature component signal and for producing an encoded and multiplexed signal; error correction means for correcting transmission errors of the encoded and multiplexed signal, for outputting a corrected multiplexed signal, and for generating a synchronization signal; a demultiplexer for demultiplexing the corrected multiplexed signal of said error correction means; a microcomputer for controlling the PLL based on the synchronization signal; and a control bus for relaying a control signal from the microcomputer to the PLL, wherein the microcomputer resets the PLL by relaying the control signal via the control bus when the error correction means indicates a loss of synchronization via the synchronization signal.
Claim 9
Dependent Claim
39 words
A digital receiver as recited in claim 5, wherein the QPSK demodulator recovers a clock signal and the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the frequency of the clock signal.
Claim 10
Dependent Claim
196 words
A receiver, comprising: a PLL (phase-locked loop) for selecting a QPSK modulated signal by generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a demodulator for demodulating the selected QPSK modulated signal and producing a demodulated signal; error correction means for correcting transmission errors in the demodulated signal and for generating a synchronization signal; a microcomputer for controlling the demodulator based on the synchronization signal; a control bus for relaying a control signal from the microcomputer to the demodulator, wherein the microcomputer resets the demodulator by relaying the control signal via the control bus when the error correction means indicates a loss of synchronization via the synchronization signal, an orthogonal detector for detecting a signal component of the selected QPSK modulated signal and for continuously performing AFC (automatic frequency control), the orthogonal detector processing the selected QPSK modulated signal prior to demodulation by the demodulator; and a demultiplexer for demultiplexing the output of said error correction means; wherein the demultiplexer produces a system clock signal and the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the frequency of the system clock signal.
Claim 11
Dependent Claim
196 words
A receiver, comprising: a PLL (phase-locked loop) for selecting a QPSK modulated signal by generating a local oscillation signal based on phase detection and comparison with a reference frequency signal; a demodulator for demodulating the selected QPSK modulated signal and producing a demodulated signal; error correction means for correcting transmission errors in the demodulated signal and for generating a synchronization signal; a microcomputer for controlling the demodulator based on the synchronization signal; a control bus for relaying a control signal from the microcomputer to the demodulator, wherein the microcomputer resets the demodulator by relaying the control signal via the control bus when the error correction means indicates a loss of synchronization via the synchronization signal, an orthogonal detector for detecting a signal component of the selected QPSK modulated signal and for continuously performing AFC (automatic frequency control), the orthogonal detector processing the selected QPSK modulated signal prior to demodulation by the demodulator; and a demultiplexer for demultiplexing the output of said error correction means; wherein the demultiplexer produces a system clock signal and the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the frequency of the system clock signal.
Claim 12
Dependent Claim
40 words
A digital receiver as recited in claim 5, wherein the demultiplexer produces a system clock signal and the reference frequency signal for phase detection and comparison by said PLL is calculated by dividing the frequency of the system clock signal.
Claim 13
Dependent Claim
165 words
A receiver for receiving a QPSK modulated signal, the receiver comprising: PLL synthesizer means for generating a local oscillation signal; orthogonal detection means for orthogonally detecting said QPSK modulated signal which is selected using said local oscillation signal; a demodulator for demodulating the detected QPSK modulated signal and producing an encoded and multiplexed signal. a demultiplexer for demultiplexing the encoded and multiplexed signal and for generating a synchronization signal; a microcomputer for controlling the demodulator based on the synchronization signal; a control bus for relaying a control signal from the microcomputer to the demodulator, wherein the microcomputer resets the demodulator by relaying the control signal via the control bus when the demultiplexer indicates a loss of synchronization via the synchronization signal, wherein AFC (automatic frequency control) is performed at said PLL synthesizer means and said orthogonal detection means when synchronization of said demultiplexer means is not established; and continuous AFC is performed at said orthogonal detection means when synchronization of said demultiplexer means is established.
Claim 14
Dependent Claim
165 words
A receiver for receiving a QPSK modulated signal, the receiver comprising: PLL synthesizer means for generating a local oscillation signal; orthogonal detection means for orthogonally detecting said QPSK modulated signal which is selected using said local oscillation signal; a demodulator for demodulating the detected QPSK modulated signal and producing an encoded and multiplexed signal. a demultiplexer for demultiplexing the encoded and multiplexed signal and for generating a synchronization signal; a microcomputer for controlling the demodulator based on the synchronization signal; a control bus for relaying a control signal from the microcomputer to the demodulator, wherein the microcomputer resets the demodulator by relaying the control signal via the control bus when the demultiplexer indicates a loss of synchronization via the synchronization signal, wherein AFC (automatic frequency control) is performed at said PLL synthesizer means and said orthogonal detection means when synchronization of said demultiplexer means is not established; and continuous AFC is performed at said orthogonal detection means when synchronization of said demultiplexer means is established.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-13 | 2003-12-13 | 2004-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-13 | 2007-12-13 | 2008-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-13 | 2011-12-13 | 2012-06-13 | $7700.00 | Window Closed / Lapsed |