US6069387A
Expired / Lapsed
US
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Lightly doped drain formation integrated with source/drain formation for high-performance transistor formation
Assignee: GlobalFoundries Inc
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Filing: 1998-04-06
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Granted: 2000-05-30
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Expires: 2018-04-06
Abstract
Abstract An integrated circuit fabrication process is provided for forming a transistor in which the source/drain areas are formed simultaneously with the lightly doped drain areas. A gate electrode including a high-K gate dielectric and a gate conductor is formed upon a semiconductor substrate. The high-K gate dielectric is then selectively narrowed relative to the gate conductor. The source/drain areas and lightly doped drain areas are formed using a single impurity implant without the need for sidewall spacers on the gate electrode. A metal silicide layer may be formed across upper surfaces of the gate conductor and source/drain areas, also without the need for sidewall spacers on the gate electrode.
Inventors
- 👤 Mark I. Gardner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:37
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D30/0227; H10D30/0229; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/693
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
51 words
A transistor comprising: an etch-stop layer formed across a semiconductor substrate; a high-K gate dielectric formed above the etch-stop layer; a gate conductor formed above the gate dielectric; lightly doped drain regions self-aligned with sidewall surfaces of the gate dielectric; and source/drain regions self-aligned with sidewall surfaces of the gate conductor.
Claim 2
Dependent Claim
51 words
A transistor comprising: an etch-stop layer formed across a semiconductor substrate; a high-K gate dielectric formed above the etch-stop layer; a gate conductor formed above the gate dielectric; lightly doped drain regions self-aligned with sidewall surfaces of the gate dielectric; and source/drain regions self-aligned with sidewall surfaces of the gate conductor.
Claim 3
Dependent Claim
26 words
The transistor of claim 1, wherein the etch-stop layer comprises a layer of silicon nitride having a thickness between about 5 angstroms and about 10 angstroms.
Claim 4
Dependent Claim
28 words
The transistor of claim 1, wherein the gate dielectric has a lateral thickness of between about 60% and about 80% of a lateral thickness of the gate conductor.
Claim 5
Dependent Claim
18 words
The transistor of claim 1, wherein the gate dielectric has a dielectric constant of greater than about 3.8.
Claim 6
Dependent Claim
35 words
The transistor of claim 1, wherein the gate dielectric comprises a material selected from the group consisting of tantalum oxide, cerium oxide, tin oxide, barium strontium titanate, lead lanthanum zirconate titanate, and barium zirconate titanate.
Claim 7
Dependent Claim
11 words
The transistor of claim 1, wherein the gate conductor comprises polysilicon.
Claim 8
Dependent Claim
21 words
The transistor of claim 6, further comprising metal silicide formed on upper surfaces of the gate conductor and the source/drain areas.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-30 | 2003-11-29 | 2004-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-30 | 2007-11-29 | 2008-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-30 | 2011-11-29 | 2012-05-30 | $7700.00 | Window Closed / Lapsed |