Multilevel interconnections of electronic components

Claim 2

A process for forming an electronic component carrier, said process comprising the steps of: providing an aluminum substrate; selectively masking said aluminum substrate; carrying out a barrier anodization process on said aluminum substrate to form a surface barrier oxide on said aluminum substrate; removing the mask; providing an upper aluminum layer over said aluminum substrate; selectively masking said upper aluminum layer; subjecting both said aluminum substrate and said upper aluminum layer to porous anodization; attaching a die to said aluminum substrate; and said die being operatively electrically connected to said aluminum substrate.

Claim 3

A process according to claim 1, wherein said die being attached to said aluminum substrate through a thermally and electrically conductive material.

Claim 4

A process according to claim 2, wherein said die being operatively electrically connected to said aluminum substrate through a plurality of wire bonds.

Claim 5

A process according to claim 3, wherein said aluminum substrate has a plurality of bond fingers, and said plurality of wire bonds are electrically connected to said plurality of bond fingers.

Claim 6

A process according to claim 2, wherein said die being operatively electrically connected to said aluminum substrate through a plurality of solder bumps.

Claim 7

A process according to claim 1, comprising a step of encapsulating said die.

Claim 8

A process according to claim 1, wherein the step of porous anodization is carried out by way of: immersing said aluminum substrate into an electrolyte at a rate of 0.4-1.0×10 -4 m/s, with the surface of said aluminum substrate substantially perpendicular to the electrolyte surface; and keeping said aluminum substrate in the electrolyte until said aluminum substrate is through-anodized.

Claim 9

A process according to claim 6, comprising a step of thermal treatment at a temperature in the range of 350-450° C.

Claim 10

A process according to claim 1, wherein said step of removal of the blocking mask and the barrier oxide comprises surface polishing.

Claim 11

A process for forming an electronic component carrier, said process comprising the steps of: providing a main aluminum layer over a substrate surface; selectively masking said main aluminum layer to define exposed areas; carrying out a barrier anodization process on said main aluminum layer to form a surface barrier oxide on the exposed areas of said main aluminum layer; removing the mask; providing an upper aluminum layer over said main aluminum layer; selectively masking said upper aluminum layer; subjecting both said main aluminum layer and said upper aluminum layer to porous anodization; attaching a die to said substrate; and said die being operatively electrically connected to said substrate.

Claim 12

A process for forming an electronic component carrier, said process comprising the steps of: providing a main aluminum layer over a substrate surface; selectively masking said main aluminum layer to define exposed areas; carrying out a barrier anodization process on said main aluminum layer to form a surface barrier oxide on the exposed areas of said main aluminum layer; removing the mask; providing an upper aluminum layer over said main aluminum layer; selectively masking said upper aluminum layer; subjecting both said main aluminum layer and said upper aluminum layer to porous anodization; attaching a die to said substrate; and said die being operatively electrically connected to said substrate.

Claim 13

A process according to claim 10, wherein said substrate being aluminum oxide.

Claim 14

A process according to claim 10, wherein said die being attached to said substrate through a thermally and electrically conductive material.

Claim 15

A process according to claim 12, wherein said die being operatively electrically connected to said substrate through a plurality of wire bonds.

Claim 16

A process according to claim 13, wherein said substrate has a plurality of bond fingers, and said plurality of wire bonds are electrically connected to said plurality of bond fingers.

Claim 17

A process according to claim 12, wherein said die being operatively electrically connected to said substrate through a plurality of solder bumps.

Claim 18

A process according to claim 10, comprising a step of encapsulating said die.

Claim 19

A process according to claim 10, wherein the step of porous anodization is carried out by way of: immersing said substrate into an electrolyte at a rate of 0.4-1.0×10 -4 m/s, with the surface of said substrate substantially perpendicular to the electrolyte surface; and keeping said substrate in the electrolyte until the aluminum is through-anodized.

Claim 20

A process according to claim 17, comprising a step of thermal treatment at a temperature in the range of 350-450° C.

Claim 21

A process according to claim 10, wherein said step of removal of the blocking mask and the barrier oxide comprises surface polishing.

Claim 22

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to an aluminum substrate and vias perpendicular to said aluminum substrate, said process comprising the steps of: defining routing layers by forming a blocking mask on said aluminum substrate, said blocking mask leaving exposed areas corresponding to said routing layers; carrying out a barrier anodization process to form a surface barrier oxide on said aluminum substrate over said routing layers; removing the blocking mask; providing an upper aluminum layer over said aluminum substrate; defining vias by forming a blocking mask on said upper aluminum layer, said blocking mask covering areas corresponding to said vias; subjecting both said aluminum substrate and said upper aluminum layer to porous anodization; attaching a die to said aluminum substrate; and said die being operatively electrically connected to said aluminum substrate.

Claim 23

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to an aluminum substrate and vias perpendicular to said aluminum substrate, said process comprising the steps of: defining routing layers by forming a blocking mask on said aluminum substrate, said blocking mask leaving exposed areas corresponding to said routing layers; carrying out a barrier anodization process to form a surface barrier oxide on said aluminum substrate over said routing layers; removing the blocking mask; providing an upper aluminum layer over said aluminum substrate; defining vias by forming a blocking mask on said upper aluminum layer, said blocking mask covering areas corresponding to said vias; subjecting both said aluminum substrate and said upper aluminum layer to porous anodization; attaching a die to said aluminum substrate; and said die being operatively electrically connected to said aluminum substrate.

Claim 24

A process according to claim 20, wherein said die being attached to said aluminum substrate through a thermally and electrically conductive material.

Claim 25

A process according to claim 21, wherein said die being operatively electrically connected to said aluminum substrate through a plurality of wire bonds.

Claim 26

A process according to claim 22 wherein said aluminum substrate has a plurality of bond fingers, and said plurality of wire bonds are electrically connected to said plurality of bond fingers.

Claim 27

A process according to claim 21, wherein said die being operatively electrically connected to said aluminum substrate through a plurality of solder bumps.

Claim 28

A process according to claim 20, comprising a step of encapsulating said die.

Claim 29

A process according to claim 20, comprising a step of defining a plurality of aluminum studs by etching aluminum oxide around said vias.

Claim 30

A process according to claim 20, comprising a step of attaching a plurality of solder balls to said vias.

Claim 31

A process according to claim 20, wherein the step of porous anodization is carried out by way of: immersing said aluminum substrate into an electrolyte at a rate of 0.4-1.0×10 -4 m/s, with the surface of said aluminum substrate substantially perpendicular to the electrolyte surface; and keeping said aluminum substrate in the electrolyte until said aluminum substrate is through-anodized.

Claim 32

A process according to claim 28, comprising a step of thermal treatment at a temperature in the range of 350-450° C.

Claim 33

A process according to claim 20, wherein the geometrical size of the surface barrier oxide defining said vias exceed those of the blocking mask formed over the surface barrier oxide defining said vias.

Claim 34

A process according to claim 20, wherein the blocking mask is a photoresist mask, and wherein said photoresist mask is smaller than said vias barrier oxide areas by a value exceeding twice the photolithographic error.

Claim 35

A process according to claim 20, wherein said step of removal of the blocking mask and the barrier oxide comprises surface polishing.

Claim 36

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to a substrate surface and vias perpendicular to said substrate, said process comprising the steps of: providing a main aluminum layer over said substrate surface; defining routing layers by forming a blocking mask on said main aluminum layer, said blocking mask leaving exposed areas corresponding to said routing layers; carrying out a barrier anodization process to form a surface barrier oxide on said main aluminum layer over said routing layers; removing the blocking mask; providing an upper aluminum layer over said main aluminum layer; defining vias by forming a blocking mask on said upper aluminum layer, said blocking mask covering areas corresponding to said vias; subjecting both said main aluminum layer and said upper aluminum layer to porous anodization; attaching a die to said substrate; and said die being operatively electrically connected to said substrate.

Claim 37

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to a substrate surface and vias perpendicular to said substrate, said process comprising the steps of: providing a main aluminum layer over said substrate surface; defining routing layers by forming a blocking mask on said main aluminum layer, said blocking mask leaving exposed areas corresponding to said routing layers; carrying out a barrier anodization process to form a surface barrier oxide on said main aluminum layer over said routing layers; removing the blocking mask; providing an upper aluminum layer over said main aluminum layer; defining vias by forming a blocking mask on said upper aluminum layer, said blocking mask covering areas corresponding to said vias; subjecting both said main aluminum layer and said upper aluminum layer to porous anodization; attaching a die to said substrate; and said die being operatively electrically connected to said substrate.

Claim 38

A process according to claim 33, wherein said substrate being aluminum oxide.

Claim 39

A process according to claim 33, wherein said die being attached to said substrate through a thermally and electrically conductive material.

Claim 40

A process according to claim 35, wherein said die being operatively electrically connected to said substrate through a plurality of wire bonds.

Claim 41

A process according to claim 36 wherein said substrate has a plurality of bond fingers, and said plurality of wire bonds are electrically connected to said plurality of bond fingers.

Claim 42

A process according to claim 35, wherein said die being operatively electrically connected to said substrate through a plurality of solder bumps.

Claim 43

A process according to claim 33, comprising a step of encapsulating said die.

Claim 44

A process according to claim 33, comprising a step of defining a plurality of aluminum studs by etching aluminum oxide around said vias.

Claim 45

A process according to claim 33, comprising a step of attaching a plurality of solder balls to said vias.

Claim 46

A process according to claim 33, wherein the step of porous anodization is carried out by way of: immersing said substrate into an electrolyte at a rate of 0.4-1.0×10 -4 m/s, with the surface of said substrate substantially perpendicular to the electrolyte surface; and keeping said substrate in the electrolyte until the aluminum is through-anodized.

Claim 47

A process according to claim 42, comprising a step of thermal treatment at a temperature in the range of 350-450° C.

Claim 48

A process according to claim 33, wherein the geometrical size of the surface barrier oxide defining said vias exceed those of the blocking mask formed over the surface barrier oxide defining said vias.

Claim 49

A process according to claim 33, wherein the blocking mask is a photoresist mask, and wherein said photoresist mask is smaller than said vias barrier oxide areas by a value exceeding twice the photolithographic error.

Claim 50

A process according to claim 33, wherein said step of removal of the blocking mask and the barrier oxide comprises surface polishing.

Claim 51

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to an aluminum substrate and vias perpendicular to said aluminum substrate, said process comprising the steps of: defining routing layers by forming a blocking mask on said aluminum substrate, said blocking mask leaving exposed areas corresponding to said routing layers, said blocking mask also leaving exposed a frame around said routing layers; carrying out a barrier anodization process on said aluminum substrate to form a surface barrier oxide over said routing layers and a surface barrier oxide defining a frame around said routing layers; removing said blocking mask; providing an upper aluminum layer over said aluminum substrate; defining vias within the area defined by the frame by providing on said upper aluminum layer a blocking mask with exposed areas defining said vias, said blocking mask leaving exposed a frame around the routing layers and vias and corresponding to the frame formed on said aluminum substrate; carrying out a barrier anodization process on said upper aluminum layer to form a surface barrier oxide defining said vias and said frame on said upper aluminum layer; forming a photoresist mask in a pattern defining vias; subjecting both said aluminum substrate and said upper aluminum layer to porous anodization; and removing the photoresist mask and surface barrier oxide over said upper aluminum layer; attaching a die to said aluminum substrate; and said die being operatively electrically connected to said aluminum substrate.

Claim 52

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to an aluminum substrate and vias perpendicular to said aluminum substrate, said process comprising the steps of: defining routing layers by forming a blocking mask on said aluminum substrate, said blocking mask leaving exposed areas corresponding to said routing layers, said blocking mask also leaving exposed a frame around said routing layers; carrying out a barrier anodization process on said aluminum substrate to form a surface barrier oxide over said routing layers and a surface barrier oxide defining a frame around said routing layers; removing said blocking mask; providing an upper aluminum layer over said aluminum substrate; defining vias within the area defined by the frame by providing on said upper aluminum layer a blocking mask with exposed areas defining said vias, said blocking mask leaving exposed a frame around the routing layers and vias and corresponding to the frame formed on said aluminum substrate; carrying out a barrier anodization process on said upper aluminum layer to form a surface barrier oxide defining said vias and said frame on said upper aluminum layer; forming a photoresist mask in a pattern defining vias; subjecting both said aluminum substrate and said upper aluminum layer to porous anodization; and removing the photoresist mask and surface barrier oxide over said upper aluminum layer; attaching a die to said aluminum substrate; and said die being operatively electrically connected to said aluminum substrate.

Claim 53

A process according to claim 47, wherein said die being attached to said aluminum substrate through a thermally and electrically conductive material.

Claim 54

A process according to claim 48, wherein said die being operatively electrically connected to said aluminum substrate through a plurality of wire bonds.

Claim 55

A process according to claim 49 wherein said aluminum substrate has a plurality of bond fingers, and said plurality of wire bonds are electrically connected to said plurality of bond fingers.

Claim 56

A process according to claim 48, wherein said die being operatively electrically connected to said aluminum substrate through a plurality of solder bumps.

Claim 57

A process according to claim 47, comprising a step of encapsulating said die.

Claim 58

A process according to claim 47, comprising a step of defining a plurality of aluminum studs by etching aluminum oxide around said vias.

Claim 59

A process according to claim 47, comprising a step of attaching a plurality of solder balls to said vias.

Claim 60

A process according to claim 47, wherein the step of porous anodization is carried out by way of: immersing said aluminum substrate into an electrolyte at a rate of 0.4-1.0×10 -4 m/s, with the surface of said aluminum substrate substantially perpendicular to the electrolyte surface; and keeping said aluminum substrate in the electrolyte until said aluminum substrate is through-anodized.

Claim 61

A process according to claim 55, comprising a step of thermal treatment at a temperature in the range of 350-450° C.

Claim 62

A process according to claim 47, wherein the blocking mask is a photoresist mask, and wherein said photoresist mask is smaller than the vias barrier oxide areas by a value exceeding twice the photolithographic error.

Claim 63

A process according to claim 57, wherein the edges of the photoresist mask are designed to be in the middle of the corresponding barrier oxide frames around the vias and routing layers.

Claim 64

A process according to claim 57, wherein the geometrical sizes of the barrier oxide over the frames around the contact pad and contact via are equal to a value exceeding twice the photolithographic error.

Claim 65

A process according to claim 47, wherein said step of removal of the blocking mask and the barrier oxide comprises surface polishing.

Claim 66

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to a substrate and vias perpendicular to said substrate, said process comprising the steps of: providing a main aluminum layer over said substrate surface; defining routing layers by forming a blocking mask on said main aluminum layer, said blocking mask leaving exposed areas corresponding to said routing layers, said blocking mask also leaving exposed a frame around said routing layers; carrying out a barrier anodization process on said main aluminum layer to form a surface barrier oxide over said routing layers and a surface barrier oxide defining a frame around said routing layers; removing said blocking mask; providing an upper aluminum layer over said main aluminum layer; defining vias within the area defined by the frame by providing on said upper aluminum layer a blocking mask with exposed areas defining said vias, said blocking mask leaving exposed a frame around the routing layers and vias and corresponding to the frame formed on said main aluminum layer; carrying out a barrier anodization process on said upper aluminum layer to form a surface barrier oxide defining said vias and said frame on said upper aluminum layer; forming a photoresist mask in a pattern defining vias; subjecting both said main aluminum layer and said upper aluminum layer to porous anodization; and removing the photoresist mask and surface barrier oxide over said upper aluminum layer; attaching a die to said substrate; and said die being operatively electrically connected to said substrate.

Claim 67

A process for forming an electronic component carrier, said electronic component carrier having routing layers parallel to a substrate and vias perpendicular to said substrate, said process comprising the steps of: providing a main aluminum layer over said substrate surface; defining routing layers by forming a blocking mask on said main aluminum layer, said blocking mask leaving exposed areas corresponding to said routing layers, said blocking mask also leaving exposed a frame around said routing layers; carrying out a barrier anodization process on said main aluminum layer to form a surface barrier oxide over said routing layers and a surface barrier oxide defining a frame around said routing layers; removing said blocking mask; providing an upper aluminum layer over said main aluminum layer; defining vias within the area defined by the frame by providing on said upper aluminum layer a blocking mask with exposed areas defining said vias, said blocking mask leaving exposed a frame around the routing layers and vias and corresponding to the frame formed on said main aluminum layer; carrying out a barrier anodization process on said upper aluminum layer to form a surface barrier oxide defining said vias and said frame on said upper aluminum layer; forming a photoresist mask in a pattern defining vias; subjecting both said main aluminum layer and said upper aluminum layer to porous anodization; and removing the photoresist mask and surface barrier oxide over said upper aluminum layer; attaching a die to said substrate; and said die being operatively electrically connected to said substrate.

Claim 68

A process according to claim 61, wherein said substrate being aluminum oxide.

Claim 69

A process according to claim 61, wherein said die being attached to said substrate through a thermally and electrically conductive material.

Claim 70

A process according to claim 63, wherein said die being operatively electrically connected to said substrate through a plurality of wire bonds.

Claim 71

A process according to claim 64 wherein said substrate has a plurality of bond fingers, and said plurality of wire bonds are electrically connected to said plurality of bond fingers.

Claim 72

A process according to claim 62, wherein said die being operatively electrically connected to said substrate through a plurality of solder bumps.

Claim 73

A process according to claim 61, comprising a step of encapsulating said die.

Claim 74

A process according to claim 61, comprising a step of defining a plurality of aluminum studs by etching aluminum oxide around said vias.

Claim 75

A process according to claim 61, comprising a step of attaching a plurality of solder balls to said vias.

Claim 76

A process according to claim 61, wherein the step of porous anodization is carried out by way of: immersing said substrate into an electrolyte at a rate of 0.4-1.0×10 -4 m/s, with the surface of said substrate substantially perpendicular to the electrolyte surface; and keeping said substrate in the electrolyte until the aluminum is through-anodized.

Claim 77

A process according to claim 70, comprising a step of thermal treatment at a temperature in the range of 350-450° C.

Claim 78

A process according to claim 61, wherein the blocking mask is a photoresist mask, and wherein said photoresist mask is smaller than the vias barrier oxide areas by a value exceeding twice the photolithographic error.

Claim 79

A process according to claim 72, wherein the edges of the photoresist mask are designed to be in the middle of the corresponding barrier oxide frames around the vias and routing layers.

Claim 80

A process according to claim 72, wherein the geometrical sizes of the barrier oxide over the frames around the contact pad and contact via are equal to a value exceeding twice the photolithographic error.

Claim 81

A process according to claim 61, wherein said step of removal of the blocking mask and the barrier oxide comprises surface polishing.