Method for testing path delay faults in sequential logic circuits

Claim 1

A method for testing for a delay fault along a signal path in a sequential circuit having at least one primary input and one primary output, said method comprising the steps of: initializing logic within the sequential circuit at a reduced clock speed with state values required to propagate a desired signal transition along the signal path of interest; propagating at the rated clock speed of the circuit said desired signal transition along said signal path of interest; and prior to propagating said desired signal transition, activating at an attempted rated clock speed said desired signal path of interest so as to allow the applied clock cycle to ramp-up to the rated clock speed of the circuit.

Claim 2

A method for testing for a delay fault along a signal path in a sequential circuit having at least one primary input and one primary output, said method comprising the steps of: initializing logic within the sequential circuit at a reduced clock speed with state values required to propagate a desired signal transition along the signal path of interest; propagating at the rated clock speed of the circuit said desired signal transition along said signal path of interest; and prior to propagating said desired signal transition, activating at an attempted rated clock speed said desired signal path of interest so as to allow the applied clock cycle to ramp-up to the rated clock speed of the circuit.

Claim 11

A method for testing for delay faults in a sequential circuit along a signal path of interest lying between a source flip-flop and a destination flip-flop, said method comprising the steps of: initializing at a reduced clock speed logic within the sequential circuit with state values required to propagate a desired signal transition along the signal path of interest from the source flip-flop to the destination flip-flop; initializing, attempted at the rated clock speed of the circuit, at least said source flip-flop with a logic value that causes said source flip-flop to generate said desired signal transition; and applying test vectors to the sequential circuit at the rated clock speed so as to propagate said desired signal transition to said destination flip-flop such that a corresponding logic value is latched therein; and comparing the logic value latched into said destination flip-flop to an expected logic value for determining whether a delay fault exists along said signal path of interest.

Claim 12

A method for testing for delay faults in a sequential circuit along a signal path of interest lying between a source flip-flop and a destination flip-flop, said method comprising the steps of: initializing at a reduced clock speed logic within the sequential circuit with state values required to propagate a desired signal transition along the signal path of interest from the source flip-flop to the destination flip-flop; initializing, attempted at the rated clock speed of the circuit, at least said source flip-flop with a logic value that causes said source flip-flop to generate said desired signal transition; and applying test vectors to the sequential circuit at the rated clock speed so as to propagate said desired signal transition to said destination flip-flop such that a corresponding logic value is latched therein; and comparing the logic value latched into said destination flip-flop to an expected logic value for determining whether a delay fault exists along said signal path of interest.

Claim 18

A method for detecting for a delay fault along a signal path of interest in a scan sequential digital circuit having primary inputs, primary outputs and a plurality of flip-flops, said method comprising the steps of: designating a source flip-flop proximate to a first end of the signal path of interest, a destination flip-flop proximate to a second end of the signal path of interest, and an initialization flip-flop extending to said source flip-flop along another signal path; switching the scan sequential digital circuit into its scan mode; applying clock cycles at a slow clock speed to initialize via a scan shift operation the initialization flip-flop and logic between the initialization flip-flop and the source flip-flop with state values required for the source flip-flop to propagate a desired signal transition to the destination flip-flop; switching the scan sequential digital circuit into its functional mode; applying a first test vector sequence to the primary input attempted at the rated clock speed so as to initialize the source flip-flop, and logic between said source flip-flop and said destination flip-flop, required to propagate said desired signal transition to said destination flip-flop; applying a second test vector sequence to the primary input at the rated clock speed such that said desired signal transition is propagated to the destination flip-flop such that a logic value is latched therein; switching the scan sequential digital circuit into its scan mode; applying clock cycles at the slow clock speed to scan out through the primary outputs the logic value latched in the destination flip-flop; and comparing the logic value latched into the destination flip-flop with an expected logic value so as to determine whether a delay fault exists along the signal path of interest.

Claim 19

A method for detecting for a delay fault along a signal path of interest in a scan sequential digital circuit having primary inputs, primary outputs and a plurality of flip-flops, said method comprising the steps of: designating a source flip-flop proximate to a first end of the signal path of interest, a destination flip-flop proximate to a second end of the signal path of interest, and an initialization flip-flop extending to said source flip-flop along another signal path; switching the scan sequential digital circuit into its scan mode; applying clock cycles at a slow clock speed to initialize via a scan shift operation the initialization flip-flop and logic between the initialization flip-flop and the source flip-flop with state values required for the source flip-flop to propagate a desired signal transition to the destination flip-flop; switching the scan sequential digital circuit into its functional mode; applying a first test vector sequence to the primary input attempted at the rated clock speed so as to initialize the source flip-flop, and logic between said source flip-flop and said destination flip-flop, required to propagate said desired signal transition to said destination flip-flop; applying a second test vector sequence to the primary input at the rated clock speed such that said desired signal transition is propagated to the destination flip-flop such that a logic value is latched therein; switching the scan sequential digital circuit into its scan mode; applying clock cycles at the slow clock speed to scan out through the primary outputs the logic value latched in the destination flip-flop; and comparing the logic value latched into the destination flip-flop with an expected logic value so as to determine whether a delay fault exists along the signal path of interest.

Claim 25

A method for detecting for delay faults in a scan sequential digital circuit having primary inputs, primary outputs and combinational logic connected between a plurality of flip-flops, said method comprising the steps of: selecting a signal path of interest; designating a source flip-flops proximate to a first end of the signal path of interest, a destination flip-flop proximate to a second end of the signal path of interest, and at least one initialization flip-flop extending to said source flip-flop along another signal path; switching the scan sequential digital circuit into its scan mode; scanning in at a slow clock speed state values to initialize the initialization flip-flop, and logic between the initialization flip-flop and the source flip-flop for the source flip-flop to propagate a desired signal transition to the destination flip-flop; switching the scan sequential digital circuit into its functional mode; applying a first test vector sequence to the primary input attempted at the rated clock speed so as to capture state values into the source flip-flop required to propagate said desired signal transition from said source flip-flop to said destination flip-flop; applying a second test vector sequence to the primary input at the rated clock speed to propagate the desired signal transition to the destination flip-flop such that a logic value is latched therein; switching the scan sequential digital circuit into its scan mode; scanning out at the slow clock speed the logic value latched in the destination flip-flop; and comparing the logic value latched into the destination flip-flop with an expected logic value so as to determine whether a delay fault exists along the signal path of interest.

Claim 26

A method for detecting for delay faults in a scan sequential digital circuit having primary inputs, primary outputs and combinational logic connected between a plurality of flip-flops, said method comprising the steps of: selecting a signal path of interest; designating a source flip-flops proximate to a first end of the signal path of interest, a destination flip-flop proximate to a second end of the signal path of interest, and at least one initialization flip-flop extending to said source flip-flop along another signal path; switching the scan sequential digital circuit into its scan mode; scanning in at a slow clock speed state values to initialize the initialization flip-flop, and logic between the initialization flip-flop and the source flip-flop for the source flip-flop to propagate a desired signal transition to the destination flip-flop; switching the scan sequential digital circuit into its functional mode; applying a first test vector sequence to the primary input attempted at the rated clock speed so as to capture state values into the source flip-flop required to propagate said desired signal transition from said source flip-flop to said destination flip-flop; applying a second test vector sequence to the primary input at the rated clock speed to propagate the desired signal transition to the destination flip-flop such that a logic value is latched therein; switching the scan sequential digital circuit into its scan mode; scanning out at the slow clock speed the logic value latched in the destination flip-flop; and comparing the logic value latched into the destination flip-flop with an expected logic value so as to determine whether a delay fault exists along the signal path of interest.