US6061810A
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US
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Computer system with error handling before reset
Assignee: Hewlett Packard Development Co LP
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Filing: 1996-12-05
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Granted: 2000-05-09
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Expires: 2016-12-05
Abstract
Abstract A computer system includes error handling hardware and software that logs the source of application program or system software errors before a reset occurs. Upon a catastrophic error, a retriggerable timer, which is periodically retriggered during normal system operation, instead times out causing a hardware reset. A predetermined time before this retriggerable timer times out, however, the microprocessor in the computer system is interrupted, and executes an interrupt routine in which it determines that the retriggerable timer is about to timeout, and logs the currently executing applications program or currently executing point in system software, as well as the actual location within the applications program or the system software. The reset subsequently occurs, but not before this information valuable for debugging and diagnosis is logged.
Inventors
- 👤 Mark R. Potter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/0706; G06F11/0721; G06F11/0766; G06F11/0772; G06F11/0787
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
104 words
A method for logging errors before a hardware reset in a microcomputer system including a microprocessor with a hardware reset input and an interrupt input, the method comprising the steps of: determining that a hardware reset will be provided to the hardware reset input; providing an interrupt to the interrupt input a predetermined period of time before the hardware reset will be provided to the hardware reset input in response to determining that a hardware reset will be provided to the hardware reset input; and executing an interrupt routine in response to said interrupt to log an error indicating operation of the interrupt routine.
Claim 2
Independent Claim
104 words
A method for logging errors before a hardware reset in a microcomputer system including a microprocessor with a hardware reset input and an interrupt input, the method comprising the steps of: determining that a hardware reset will be provided to the hardware reset input; providing an interrupt to the interrupt input a predetermined period of time before the hardware reset will be provided to the hardware reset input in response to determining that a hardware reset will be provided to the hardware reset input; and executing an interrupt routine in response to said interrupt to log an error indicating operation of the interrupt routine.
Claim 3
Dependent Claim
94 words
The method of claim 1, wherein the microcomputer system further includes a reloadable timer with an indicator of time remaining until timeout, and wherein said step of determining that a hardware reset will be provided to the hardware reset input further comprises the steps of: periodically reloading the reloadable timer during normal operation of the microcomputer system; and if the indicator of time remaining until timeout falls below a predetermined threshold, indicating that it is determined that a hardware reset will be provided to the hardware reset input within the predetermined period of time.
Claim 4
Dependent Claim
98 words
The method of claim 1, wherein the microcomputer system further includes a reloadable timer and a delay timer with an output coupled to the microcomputer hardware reset input, and wherein said step of determining that a hardware reset will be provided to the hardware reset input further comprises the steps of: periodically reloading the reloadable timer during normal operation of the microcomputer system; and if the reloadable timer times out, indicating that it is determined that a hardware reset will be provided to the hardware reset input within the predetermined period of time and starting the delay timer.
Claim 5
Dependent Claim
49 words
The method of claim 1, wherein said step of executing an interrupt routine further comprises the steps of: determining the address where the microprocessor was executing when said interrupt was provided to the microprocessor; and logging a message indicative of where it was determined that the microprocessor was executing.
Claim 6
Dependent Claim
64 words
The method of claim 4, wherein the microcomputer system is running an operating system that maintains a list of loaded modules and wherein said step of determining the address further comprises the step of: determining if and which of currently loaded modules was executing; and wherein said step of logging further comprises the step of: logging the determined loaded module's name and execution address.
Claim 7
Dependent Claim
56 words
The method of claim 5, wherein the operating system is Netware and wherein said step of determining the address further comprises the step of: determining if and which of currently loaded Netware Loadable Modules was executing; and wherein said step of logging further comprises the step of: logging the Netware Loadable Module name and execution address.
Claim 8
Dependent Claim
24 words
The method of claim 4, wherein said step of logging further comprises the step of: writing said message to a non-volatile random access memory.
Claim 9
Dependent Claim
24 words
The method of claim 1, wherein said step of providing an interrupt further comprises the step of: providing a non-maskable interrupt to the microprocessor.
Claim 10
Dependent Claim
153 words
A computer system that logs errors before a hardware reset, comprising: a bus with data, address, and control lines; a microprocessor with a reset input and an interrupt input, said microprocessor coupled to said bus; a mass storage subsystem coupled to said bus for providing data to and storing data from said microprocessor over said bus; a software module for periodic execution by said microprocessor, said software module, when periodically executed, periodically performs a predetermined operation; a timer circuit providing a reset signal to the reset input in response to said software module failing to periodically perform the predetermined operation; an interrupt circuit for providing an interrupt signal to the interrupt input a predetermined period of time before said timer circuit provides the reset signal; and an error logging software module for execution by said microprocessor in response to the interrupt signal, said error logging software module, when executed, logging an error message.
Claim 11
Dependent Claim
153 words
A computer system that logs errors before a hardware reset, comprising: a bus with data, address, and control lines; a microprocessor with a reset input and an interrupt input, said microprocessor coupled to said bus; a mass storage subsystem coupled to said bus for providing data to and storing data from said microprocessor over said bus; a software module for periodic execution by said microprocessor, said software module, when periodically executed, periodically performs a predetermined operation; a timer circuit providing a reset signal to the reset input in response to said software module failing to periodically perform the predetermined operation; an interrupt circuit for providing an interrupt signal to the interrupt input a predetermined period of time before said timer circuit provides the reset signal; and an error logging software module for execution by said microprocessor in response to the interrupt signal, said error logging software module, when executed, logging an error message.
Claim 12
Dependent Claim
47 words
The computer system of claim 9, wherein said error logging software module further comprises: address determining code that, when executed, determines an address at which said microprocessor was executing when the interrupt signal was provided; and logging code that, when executed, logs a message indicating the address.
Claim 13
Dependent Claim
31 words
The computer system of claim 10, wherein the computer includes a semi-permanent memory, wherein said error logging software module further comprises: code for writing the error message to the semi-permanent memory.
Claim 14
Dependent Claim
31 words
The computer system of claim 9, wherein the computer includes a semi-permanent memory, wherein said error logging software module further comprises: code for writing the error message to the semi-permanent memory.
Claim 15
Dependent Claim
27 words
The computer system of claim 9, wherein the computer system runs the Netware Operating System, and wherein said error logging software module is a Netware Loadable Module.
Claim 16
Dependent Claim
65 words
The computer system of claim 9, wherein the computer system runs an operating system that includes a list of loaded modules, and wherein said error logging software module further comprises: module determining code for determining if and which of currently loaded modules was executing when the interrupt was provided; and code for writing an error message containing the name of the determined executing loaded module.
Claim 17
Dependent Claim
63 words
The computer system of claim 9, wherein the computer system runs the Netware Operating System, and wherein said error logging software module further comprises: Netware module determining code for determining if and which of currently loaded Netware Loadable Modules was executing when said interrupt signal was provided; and code for writing an error message containing the name of the determined executing loaded module.
Claim 18
Dependent Claim
36 words
The computer system of claim 9 further comprising: a network interface card coupled to said bus for communication with a network; and a memory subsystem coupled to said bus for providing memory storage for said microprocessor.
Claim 19
Dependent Claim
37 words
The computer system of claim 9, wherein said timer circuit includes: a reloadable timer with an indicator of time remaining until timeout, wherein said interrupt circuit is responsive to the indicator indicating the predetermined period of time.
Claim 20
Dependent Claim
14 words
The computer system of claim 17, wherein the predetermined operation reloads the reloadable timer.
Claim 21
Dependent Claim
61 words
The computer system of claim 9, wherein said timer circuit includes: a reloadable timer; and a delay timer responsive to a timeout of the reloadable timer and for providing the reset signal to the reset input the predetermined period of time after the timeout of the reloadable timer, wherein said interrupt circuit is responsive to the timeout of the reloadable timer.
Claim 22
Dependent Claim
13 words
The computer system of 19, wherein the predetermined operation reloads the reloadable timer.
Claim 23
Dependent Claim
13 words
The computer system of 19, wherein the predetermined operation reloads the reloadable timer.
Claim 24
Dependent Claim
15 words
The computer system of claim 9, wherein the interrupt signal is a non-maskable interrupt signal.
References Cited (Backward Citations)
EP0051920A2
Cited
US4803682A
Cited
EP0260568A2
Cited
US4982404A
Cited
US5041962A
Cited
US5251227A
Cited
EP0428917A2
Cited
EP0440451A2
Cited
US5139473A
Cited
US5333285A
Cited
US5390324A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |