US6061285A
Expired / Lapsed
US
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Semiconductor memory device capable of executing earlier command operation in test mode
Assignee: Renesas Electronics Corp
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Filing: 1999-11-10
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Granted: 2000-05-09
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Expires: 2019-11-10
Abstract
Abstract An SDRAM includes a test precharge signal generator which is activated in response to a test mode signal from a test mode detector. The test precharge signal generator generates a test precharge signal before generation of a precharge signal by a command decoder in response to a write signal from the command decoder. Therefore, in the wafer test using a clock signal having low frequency, it becomes possible to execute precharging operation before the input of the normal precharge command after the input of the write command. As a result, it becomes possible to replace a memory cell, which has low power in terms of write recovery time period, by a redundant memory cell in the wafer test, and to improve production yield.
Inventors
- 👤 Yasuhiko Tsukikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:35
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/14
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
143 words
A semiconductor memory device having a normal mode and a test mode, comprising: a memory cell array; a command decoder decoding a first command comprising a first combination of a plurality of external signals and a second command comprising a second combination of said plurality of external signals and applied after said first command, and generating first and second command signals, respectively; an operation circuit coupled to said memory cell array and executing the first and second command operations in response to said first and second command signals; and an early activation circuit coupled to said command decoder and said operation circuit, and activating said second command signal which is to be applied from said command decoder to said operation circuit, before generation of said second command signal by said command decoder, in response to said first command signal in said test mode.
Claim 2
Dependent Claim
143 words
A semiconductor memory device having a normal mode and a test mode, comprising: a memory cell array; a command decoder decoding a first command comprising a first combination of a plurality of external signals and a second command comprising a second combination of said plurality of external signals and applied after said first command, and generating first and second command signals, respectively; an operation circuit coupled to said memory cell array and executing the first and second command operations in response to said first and second command signals; and an early activation circuit coupled to said command decoder and said operation circuit, and activating said second command signal which is to be applied from said command decoder to said operation circuit, before generation of said second command signal by said command decoder, in response to said first command signal in said test mode.
Claim 3
Dependent Claim
33 words
The semiconductor memory device according to claim 1, wherein said second command is a precharge command, said second command signal is a precharge signal and said second command operation is a precharging operation.
Claim 4
Dependent Claim
48 words
The semiconductor memory device according to claim 2, wherein said operation circuit includes a data write circuit writing data to said memory cell array, said first command is a write command, said first command signal is a write signal, and said first command operation is a write operation.
Claim 5
Dependent Claim
35 words
The semiconductor memory device according to claim 3, wherein said external signal includes a write enable signal, and said early activation circuit activates said precharge signal in response to inactivation of said write enable signal.
Claim 6
Dependent Claim
48 words
The semiconductor memory device according to claim 2, wherein said operation circuit includes a data read circuit reading data from said memory cell array, said first command is a read command, said first command signal is a read signal and said first command operation is a read operation.
Claim 7
Dependent Claim
37 words
The semiconductor memory device according to claim 5, wherein said external signal includes a column address strobe signal, and said early activation circuit activates said precharge signal in response to inactivation of said column address strobe signal.
Claim 8
Dependent Claim
33 words
The semiconductor memory device according to claim 2, wherein said first command is an activation command, said fist command signal is an activation signal and said first command operation is an activating operation.
Claim 9
Dependent Claim
37 words
The semiconductor memory device according to claim 7, wherein said external signal includes a row address strobe signal, and said early activation circuit activates said precharge signal in response to inactivation of said row address strobe signal.
Claim 10
Dependent Claim
38 words
The semiconductor memory device according to claim 2, further comprising a test mode detecting circuit detecting said test mode and generating a test mode signal for activating said early activation circuit, in response to an externally applied signal.
Claim 11
Dependent Claim
83 words
The semiconductor memory device according to claim 9, wherein said early activation circuit includes a flip-flop set in response to said first command signal and reset in response to one of said external signals, a logic circuit allowing signal input to said flip-flop in response to said test mode signal, a one shot multivibrator generating a test precharge signal in response to an output signal of said flip-flop, and a logic gate activating said precharge signal in response to said test precharge signal.
Claim 12
Dependent Claim
30 words
The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a synchronous dynamic random access memory device operating in synchronization with an externally applied clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |