US6061267A
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Memory circuits, systems, and methods with cells using back bias to control the threshold voltage of one or more corresponding cell transistors
Assignee: Texas Instruments Inc
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Filing: 1998-09-28
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Granted: 2000-05-09
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Expires: 2018-09-28
Abstract
Abstract A memory configuration (20). The memory configuration comprises a plurality of memory cells (SCI1, SCI2, SCI3) arranged in a plurality of rows and columns. The memory configuration also comprises a plurality of wordlines (WL 0 -WL N ). Each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period. In addition, each of the plurality of memory cells comprises at least one transistor (e.g., AT3) coupled to receive a back bias. The memory configuration also comprises circuitry for providing a first back bias operable to cause only the at least one transistor in each of the memory cells in the selected row (e.g., WL 0 ) to have a first threshold voltage, and circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some of the non-selected rows to have a second threshold voltage. The first threshold voltage is different than the second threshold voltage.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
202 words
A memory configuration, comprising: a memory array comprising a plurality of memory cells arranged in a plurality of rows and columns; a plurality of wordlines, wherein each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period, wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias; circuitry for providing a first back bias operable to cause the at least one transistor in each of the memory cells in the selected row to have a first threshold voltage; circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some of the non-selected rows to have a second threshold voltage during the period; wherein the first threshold voltage is different than the second threshold voltage; and wherein the at least one transistor coupled to receive the back bias is coupled to receive the back bias from a buried wordline corresponding to the row.
Claim 2
Dependent Claim
202 words
A memory configuration, comprising: a memory array comprising a plurality of memory cells arranged in a plurality of rows and columns; a plurality of wordlines, wherein each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period, wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias; circuitry for providing a first back bias operable to cause the at least one transistor in each of the memory cells in the selected row to have a first threshold voltage; circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some of the non-selected rows to have a second threshold voltage during the period; wherein the first threshold voltage is different than the second threshold voltage; and wherein the at least one transistor coupled to receive the back bias is coupled to receive the back bias from a buried wordline corresponding to the row.
Claim 3
Dependent Claim
20 words
The memory configuration of claim 1 wherein the buried wordline is electrically connected to the wordline corresponding to the row.
Claim 4
Dependent Claim
20 words
The memory configuration of claim 1 wherein the buried wordline is electrically disconnected from the wordline corresponding to the row.
Claim 5
Dependent Claim
72 words
A memory configuration, comprising: an array comprising a plurality of memory cells arranged in a plurality of rows and columns; a plurality of wordlines, wherein each of the plurality of wordlines corresponds to one of the plurality of rows; and wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias from a wordline corresponding to the row on which the cell is arranged.
Claim 6
Dependent Claim
72 words
A memory configuration, comprising: an array comprising a plurality of memory cells arranged in a plurality of rows and columns; a plurality of wordlines, wherein each of the plurality of wordlines corresponds to one of the plurality of rows; and wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias from a wordline corresponding to the row on which the cell is arranged.
Claim 7
Dependent Claim
16 words
The memory configuration of claim 4 wherein the at least one transistor comprises an access transistor.
Claim 8
Dependent Claim
16 words
The memory configuration of claim 4 wherein the at least one transistor comprises a drive transistor.
Claim 9
Dependent Claim
16 words
The memory configuration of claim 4 wherein the at least one transistor comprises a pull-up transistor.
Claim 10
Dependent Claim
22 words
The memory configuration of claim 4 wherein the at least one transistor comprises each of an access transistor and a drive transistor.
Claim 11
Dependent Claim
23 words
The memory configuration of claim 4 wherein the at least one transistor is coupled to receive the back bias via a direct connection.
Claim 12
Dependent Claim
23 words
The memory configuration of claim 4 wherein the at least one transistor is coupled to receive the back bias via a dielectric coupling.
Claim 13
Dependent Claim
202 words
A memory configuration, comprising: a memory array comprising a plurality of memory cells arranged in a plurality of rows and columns; a plurality of wordlines, wherein each of the plurality or wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period, wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias; circuitry for providing a first back bias operable to cause the at least one transistor in the each of the memory cells in the selected row to have a first threshold voltage; circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some on the non-selected rows to have a second threshold voltage during the period; wherein the first threshold voltage is different than the second threshold voltage; and wherein the at least one transistor coupled to receive the back bias is coupled to receive the back bias from the wordline corresponding to the row.
Claim 14
Dependent Claim
202 words
A memory configuration, comprising: a memory array comprising a plurality of memory cells arranged in a plurality of rows and columns; a plurality of wordlines, wherein each of the plurality or wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period, wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias; circuitry for providing a first back bias operable to cause the at least one transistor in the each of the memory cells in the selected row to have a first threshold voltage; circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some on the non-selected rows to have a second threshold voltage during the period; wherein the first threshold voltage is different than the second threshold voltage; and wherein the at least one transistor coupled to receive the back bias is coupled to receive the back bias from the wordline corresponding to the row.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |