US6058044A
Expired / Lapsed
US
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Shielded bit line sensing scheme for nonvolatile semiconductor memory
Assignee: Toshiba Corp
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Filing: 1998-12-09
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Granted: 2000-05-02
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Expires: 2018-12-09
Abstract
Abstract A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.
Inventors
- 👤 Yoshihisa Sugiura
- 👤 Yoshihisa Iwata
- 👤 Hiroshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/04; G11C16/0483
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
200 words
A nonvolatile semiconductor memory comprising: a memory cell array having first and second memory cells; a word line commonly connected to control gates of the first and the second memory cells; a first bit line connected to a drain-side node of the first memory cell; a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line; a switch circuit operated in a first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in a second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and a decoder for selecting the word line, outputting data in the first memory cell to the first bit line in the first data read and outputting data in the second memory cell to the second bit line in the second data read.
Claim 2
Dependent Claim
200 words
A nonvolatile semiconductor memory comprising: a memory cell array having first and second memory cells; a word line commonly connected to control gates of the first and the second memory cells; a first bit line connected to a drain-side node of the first memory cell; a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line; a switch circuit operated in a first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in a second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and a decoder for selecting the word line, outputting data in the first memory cell to the first bit line in the first data read and outputting data in the second memory cell to the second bit line in the second data read.
Claim 3
Dependent Claim
27 words
A nonvolatile semiconductor memory according to claim 1, wherein the precharge potential and the positive potential are substantially simultaneously applied to the first and second bit lines.
Claim 4
Dependent Claim
21 words
A nonvolatile semiconductor memory according to claim 1, wherein the precharge potential and the positive potential are equal to each other.
Claim 5
Dependent Claim
39 words
A nonvolatile semiconductor memory according to claim 1, wherein each of the precharge potential and the positive potential is a power source potential which is substantially simultaneously applied to the first and second bit lines from a power source.
Claim 6
Dependent Claim
30 words
A nonvolatile semiconductor memory according to claim 1, further comprising a latch circuit connected to the first and the second bit lines and having a function of a sense amplifier.
Claim 7
Dependent Claim
114 words
A nonvolatile semiconductor memory comprising: a memory cell array having first and second memory cells, the first memory cell being disposed adjacent to the second memory cell; a word line commonly connected to control gates of the first and second memory cells; a first bit line connected to a drain-side node of the first memory cell; a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line; a first source line connected to a source-side node of the first memory cell; and a second source line connected to a source-side node of the second memory cell and isolated from the first source line.
Claim 8
Dependent Claim
114 words
A nonvolatile semiconductor memory comprising: a memory cell array having first and second memory cells, the first memory cell being disposed adjacent to the second memory cell; a word line commonly connected to control gates of the first and second memory cells; a first bit line connected to a drain-side node of the first memory cell; a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line; a first source line connected to a source-side node of the first memory cell; and a second source line connected to a source-side node of the second memory cell and isolated from the first source line.
Claim 9
Dependent Claim
98 words
A nonvolatile semiconductor memory according to claim 6, further comprising a source line decoder operated in a first data read outputting data of the first memory cell in such a manner as to set the second source line to a positive potential and set the first source line to a low potential which is lower than the positive potential and operated in a second data read outputting data of the second memory cell in such a manner as to set the first source line to the positive potential and set the second source line to the low potential.
Claim 10
Dependent Claim
146 words
A nonvolatile semiconductor memory according to claim 7, further comprising a switch circuit structured to be operated in the first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in the second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and a decoder for selecting the word line, outputting data of the first memory cell to the first bit line in the first data read and outputting data of the second memory cell to the second bit line in the second data read.
Claim 11
Dependent Claim
31 words
A nonvolatile semiconductor memory according to claim 8, wherein each of the precharge potential and the positive potential is a power source potential and the low potential is a ground potential.
Claim 12
Dependent Claim
31 words
A nonvolatile semiconductor memory according to claim 6, wherein the source-side node of the first memory cell and the source-side node of the second memory cell are isolated from each other.
Claim 13
Dependent Claim
221 words
A nonvolatile semiconductor memory comprising: first and second NAND cell units constituted by NAND columns having a plurality of memory cells connected to one another in series and two select transistors each of which is connected to of both ends of the NAND columns; a first bit line connected to a drain-side node of the first NAND cell unit; a second bit line connected to a drain-side node of the second NAND cell unit and disposed adjacent to the first bit line; a switch circuit operated in a first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in a second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and a decoder for outputting data of one memory cell in the first NAND cell units to the first bit line in the first data read and outputting data of one memory cell in the second NAND cell units to the second bit line in the second data read.
Claim 14
Dependent Claim
221 words
A nonvolatile semiconductor memory comprising: first and second NAND cell units constituted by NAND columns having a plurality of memory cells connected to one another in series and two select transistors each of which is connected to of both ends of the NAND columns; a first bit line connected to a drain-side node of the first NAND cell unit; a second bit line connected to a drain-side node of the second NAND cell unit and disposed adjacent to the first bit line; a switch circuit operated in a first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in a second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and a decoder for outputting data of one memory cell in the first NAND cell units to the first bit line in the first data read and outputting data of one memory cell in the second NAND cell units to the second bit line in the second data read.
Claim 15
Dependent Claim
48 words
A nonvolatile semiconductor memory according to claim 11, further comprising a first source line connected to a source-side node of the first NAND cell unit; and a second source line connected to a source-side node of the second NAND cell unit and isolated from the first source line.
Claim 16
Dependent Claim
84 words
A nonvolatile semiconductor memory according to claim 12, further comprising a source line decoder operated in the first data read in such a manner as to set the second source line to the positive potential and set the first source line to a low potential which is lower than the positive potential and operated in the second data read in such a manner as to set the first source line to the positive potential and set the second source line to the low potential.
Claim 17
Dependent Claim
31 words
A nonvolatile semiconductor memory according to claim 13, wherein each of the precharge potential and the positive potential is a power source potential and the low potential is a ground potential.
Claim 18
Dependent Claim
31 words
A nonvolatile semiconductor memory according to claim 12, wherein the source-side node of the first memory cell and the source-side node of the second memory cell are isolated from each other.
Claim 19
Dependent Claim
45 words
A nonvolatile semiconductor memory according to claim 12, wherein the first NAND cell unit and the second NAND cell unit are isolated from each other by a device isolation film having a line pattern extending substantially in parallel with the first and second bit lines.
Claim 20
Dependent Claim
172 words
A data read method of a nonvolatile semiconductor memory having a word line commonly connected to control gates of first and second memory cells, a first bit line connected to a drain-side node of the first memory cell and a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line, comprising the steps of: precharging the first bit line to a precharge potential followed by bringing the first bit line to a floating state and outputting data of the first memory cell to the first bit line in a state in which the second bit line is fixed to a positive potential in a first data read; and precharging the second bit line to the precharge potential followed by bringing the second bit line to the floating state and outputting data of the second memory cell to the second bit line in a state in which the first bit line is fixed to the positive potential in a second data read.
Claim 21
Dependent Claim
172 words
A data read method of a nonvolatile semiconductor memory having a word line commonly connected to control gates of first and second memory cells, a first bit line connected to a drain-side node of the first memory cell and a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line, comprising the steps of: precharging the first bit line to a precharge potential followed by bringing the first bit line to a floating state and outputting data of the first memory cell to the first bit line in a state in which the second bit line is fixed to a positive potential in a first data read; and precharging the second bit line to the precharge potential followed by bringing the second bit line to the floating state and outputting data of the second memory cell to the second bit line in a state in which the first bit line is fixed to the positive potential in a second data read.
Claim 22
Dependent Claim
94 words
A data read method according to claim 17, wherein a period of time in which the precharge potential is applied to the first bit line and a period of time in which the positive potential is applied to the second bit line are substantially the same in the first data read, and a period of time in which the precharge potential is applied to the second bit line and a period of time in which the positive potential is applied to the first bit line are substantially the same in the second data read.
Claim 23
Dependent Claim
52 words
A data read method according to claim 17, wherein each of the precharge potential and the positive potential is a power source potential, and the power source potential is simultaneously applied to the first and second bit lines from a power source in the first data read and the second data read.
Claim 24
Dependent Claim
85 words
A data read method according to claim 17, wherein the positive potential is applied to a source-side node of the second memory cell and a low potential which is lower than the positive potential is applied to a source-side node of the first memory cell in the first data read, and the positive potential is applied to a source-side node of the first memory cell and the low potential is applied to a source-side node of the second memory cell in the second data read.
Claim 25
Dependent Claim
31 words
A data read method according to claim 20, wherein each of the precharge potential and the positive potential is a power source potential, and the low potential is a ground potential.
Claim 26
Dependent Claim
170 words
A data read method of a nonvolatile semiconductor memory having a first bit line connected to a drain-side node of a first NAND cell unit and a second bit line connected to a drain-side node of a second NAND cell unit and disposed adjacent to the first bit line, comprising the steps of: precharging the first bit line to a precharge potential followed by bringing the first bit line to a floating state and outputting data of one memory cell of the first NAND cell unit to the first bit line in a state in which the second bit line is fixed to a positive potential in a first data read, and precharging the second bit line to the precharge potential followed by bringing the second bit line to the floating state and outputting data of one memory cell in the second NAND cell unit to the second bit line in a state in which the first bit line is fixed to the positive potential in a second data read.
Claim 27
Dependent Claim
170 words
A data read method of a nonvolatile semiconductor memory having a first bit line connected to a drain-side node of a first NAND cell unit and a second bit line connected to a drain-side node of a second NAND cell unit and disposed adjacent to the first bit line, comprising the steps of: precharging the first bit line to a precharge potential followed by bringing the first bit line to a floating state and outputting data of one memory cell of the first NAND cell unit to the first bit line in a state in which the second bit line is fixed to a positive potential in a first data read, and precharging the second bit line to the precharge potential followed by bringing the second bit line to the floating state and outputting data of one memory cell in the second NAND cell unit to the second bit line in a state in which the first bit line is fixed to the positive potential in a second data read.
Claim 28
Dependent Claim
94 words
A data read method according to claim 22, wherein a period of time in which the precharge potential is applied to the first bit line and a period of time in which the positive potential is applied to the second bit line are substantially the same in the first data read, and a period of time in which the precharge potential is applied to the second bit line and a period of time in which the positive potential is applied to the first bit line are substantially the same in the second data read.
Claim 29
Dependent Claim
52 words
A data read method according to claim 22, wherein each of the precharge potential and the positive potential is a power source potential, and the power source potential is simultaneously applied to the first and second bit lines from a power source in the first data read and the second data read.
Claim 30
Dependent Claim
89 words
A data read method according to claim 22, wherein the positive potential is applied to a source-side node of the second NAND cell unit and a low potential which is lower than the positive potential is applied to a source-side node of the first NAND cell unit in the first data read, and the positive potential is applied to a source-side node of the first NAND cell unit and the low potential is applied to a source-side node of the second NAND cell unit in the second data read.
Claim 31
Dependent Claim
31 words
A data read method according to claim 25, wherein each of the precharge potential and the positive potential is a power source potential, and the low potential is a ground potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-02 | 2003-11-01 | 2004-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-02 | 2007-11-01 | 2008-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-02 | 2011-11-01 | 2012-05-02 | $7700.00 | Window Closed / Lapsed |