US6054899A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic gain control circuit with low distortion
Assignee: Industrial Technology Research Institute
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Filing: 1999-01-22
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Granted: 2000-04-25
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Expires: 2019-01-22
Abstract
Abstract An automatic gain control circuit is described, comprising: a resistance control node, a first field-effect transistor, a second field-effect transistor, an inductor, a first resistor, a second resistor, a first capacitor, and a second capacitor. The inductor is connected in series with the field-effect transistors. The first resistor is connected between the gate of the first field-effect transistor and the resistance control node while the second resistor is connected between the gate of the second field-effect transistor and the resistance control node. The first capacitor is connected between the gate and drain of the first field-effect transistor, whereas the second capacitor is connected between the gate and source of the second field-effect transistor.
Inventors
- 👤 Ling-Wei Ke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:55
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/007
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
103 words
An automatic gain control circuit, comprising: a resistance control node; a first field-effect transistor and a second field-effect transistor; an inductor connected between a source of said first field-effect transistor and a drain of said second field-effect transistor; a first resistor connected between a gate of said first field-effect transistor and said resistance control node; a second resistor connected between a gate of said second field-effect transistor and said resistance control node; a first capacitor connected between said gate and a drain of said first field-effect transistor; and a second capacitor connected between said gate and a source of said second field-effect transistor.
Claim 2
Dependent Claim
103 words
An automatic gain control circuit, comprising: a resistance control node; a first field-effect transistor and a second field-effect transistor; an inductor connected between a source of said first field-effect transistor and a drain of said second field-effect transistor; a first resistor connected between a gate of said first field-effect transistor and said resistance control node; a second resistor connected between a gate of said second field-effect transistor and said resistance control node; a first capacitor connected between said gate and a drain of said first field-effect transistor; and a second capacitor connected between said gate and a source of said second field-effect transistor.
Claim 3
Dependent Claim
30 words
The automatic gain control circuit as claimed in claim 1, wherein said first capacitor has an impedance less than the resistance of said first resistor when operating at RF frequency.
Claim 4
Dependent Claim
28 words
The automatic gain control circuit as claimed in claim 2, wherein said impedance of said first capacitor is greater than the channel resistance of said first field-effect transistor.
Claim 5
Dependent Claim
30 words
The automatic gain control circuit as claimed in claim 1, wherein said second capacitor has an impedance less than the resistance of said second resistor when operating at RF frequency.
Claim 6
Dependent Claim
28 words
The automatic gain control circuit as claimed in claim 4, wherein said impedance of said second capacitor is greater than the channel resistance of said second field-effect transistor.
Claim 7
Dependent Claim
21 words
The automatic gain control circuit as claimed in claim 1, wherein said first capacitor and said second capacitor have matched capacitances.
Claim 8
Dependent Claim
24 words
The automatic gain control circuit as claimed in claim 1, wherein said first field-effect transistor and said second field-effect transistor have symmetrically matched structures.
Claim 9
Dependent Claim
34 words
The automatic gain control circuit as claimed in claim 1, wherein said inductor has an impedance greater than the channel resistance of said field-effect transistors when operating at a frequency higher than RF frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-25 | 2003-10-25 | 2004-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-25 | 2007-10-25 | 2008-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-25 | 2011-10-25 | 2012-04-25 | $7700.00 | Window Closed / Lapsed |