US6049662A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for model size reduction of an integrated circuit utilizing net invariants
Assignee: International Business Machines Corp
•
Filing: 1997-01-27
•
Granted: 2000-04-11
•
Expires: 2017-01-27
Abstract
Abstract The present invention provides a system and method for verifying an integrated circuit model. The model includes a plurality of net variables. The system and method comprises generating a plurality of tests for simulating the integrated circuit, precalculating a reduced model based upon the generated tests, and evaluating the reduced model. In a preferred embodiment, the present invention includes restricting the test that are generated. Then net invariants for the integrated circuit are generated by translating the restricted plurality of tests to a smaller set of possible values for the net variables. Thereafter, a minimization algorithm or procedure is utilized to minimize the logic used in the particular system based upon the latch constraints. This system produces a reduced model which reduces the amount of the integrated circuit that must be simulated thereby increasing the simulation speed thereof. Accordingly, the present invention integrates an event-driven simulation and a cycle simulation in such a manner that the saving can be proportional to the size of the reduction of the model. In many environments this reduction is significant because it allows for a significant reduction in space which has a clear bearing on the verification process.
Inventors
- 👤 Avijit Saha
- 👤 James D. Christian
- 👤 William M. Canfield
- 👤 Greg N. Fife
- 👤 Nadeem Malik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
67 words
A method for verifying an integrated circuit model via simulation comprising the steps of: (a) precalculating a reduced model based upon net invariants of the integrated circuit, wherein the net invariants are based upon a restricted plurality of tests based on characteristics of the integrated circuit; and (b) evaluating the reduced model using cycle simulation wherein all gates in the reduced model is evaluated for each cycle.
Claim 2
Independent Claim
67 words
A method for verifying an integrated circuit model via simulation comprising the steps of: (a) precalculating a reduced model based upon net invariants of the integrated circuit, wherein the net invariants are based upon a restricted plurality of tests based on characteristics of the integrated circuit; and (b) evaluating the reduced model using cycle simulation wherein all gates in the reduced model is evaluated for each cycle.
Claim 3
Dependent Claim
20 words
The method of claim 1 which includes the step of providing a plurality of tests for simulating the integrated circuit.
Claim 4
Dependent Claim
63 words
The method of claim 2 in which the precalculating step (a) comprises the steps of: (a1) restricting the plurality of tests based on the characteristics of the integrated circuit to provide a restricted plurality of tests; (a2) providing a plurality of net invariants based upon the restricted plurality of tests; and (a3) minimizing the integrated circuit model size based upon the net invariants.
Claim 5
Dependent Claim
18 words
The method of claim 3 in which the restricting step (a1) comprises partitioning the tests into predetermined categories.
Claim 6
Dependent Claim
27 words
The method of claim 4 in which the providing step (a2) comprises providing the net invariants as constraints of the output of latches of the integrated circuit.
Claim 7
Independent Claim
97 words
A method for reducing a model size of integrated circuit model comprising the steps of: (a) generating a plurality of tests for simulating the integrated circuit; (b) restricting the plurality of tests based on the characteristics of the integrated circuit to provide a restricted plurality of tests; (c) providing a plurality of net invariants based upon the restricted plurality of tests; (d) minimizing the integrated circuit model size based upon the net invariants; (e) evaluating the minimized integrated circuit model using cycle simulation wherein all gates in the minimized integrated circuit model is evaluated for each cycle.
Claim 8
Independent Claim
97 words
A method for reducing a model size of integrated circuit model comprising the steps of: (a) generating a plurality of tests for simulating the integrated circuit; (b) restricting the plurality of tests based on the characteristics of the integrated circuit to provide a restricted plurality of tests; (c) providing a plurality of net invariants based upon the restricted plurality of tests; (d) minimizing the integrated circuit model size based upon the net invariants; (e) evaluating the minimized integrated circuit model using cycle simulation wherein all gates in the minimized integrated circuit model is evaluated for each cycle.
Claim 9
Dependent Claim
18 words
The method of claim 6 in which the restricting step (b) comprises partitioning the tests into predetermined categories.
Claim 10
Dependent Claim
27 words
The method of claim 7 in which the providing step (c) comprises providing the net invariants as constraints of the output of latches of the integrated circuit.
Claim 11
Dependent Claim
33 words
The method of claim 6 in which step c) includes the step of generating invariants by translating the restricted plurality of tests to a smaller set of possible values for the net variables.
Claim 12
Independent Claim
66 words
A system for verifying an integrated circuit model via simulation comprising: means for precalculating a reduced model based upon net invariants of the integrated circuit, wherein the net invariants are based upon a restricted plurality of tests based on characteristics of the integrated circuit; and means for evaluating the reduced model using cycle simulation wherein all gates in the reduced model is evaluated for each cycle.
Claim 13
Independent Claim
66 words
A system for verifying an integrated circuit model via simulation comprising: means for precalculating a reduced model based upon net invariants of the integrated circuit, wherein the net invariants are based upon a restricted plurality of tests based on characteristics of the integrated circuit; and means for evaluating the reduced model using cycle simulation wherein all gates in the reduced model is evaluated for each cycle.
Claim 14
Dependent Claim
20 words
The system of claim 10 which includes a means for providing a plurality of tests for simulating the integrated circuit.
Claim 15
Dependent Claim
62 words
The system of claim 10 in which the precalculating means comprises: means for restricting the plurality of tests based on the characteristics of the integrated circuit to provide a restricted plurality of tests; means for providing a plurality of net invariants based upon the restricted plurality of tests; and means for minimizing the integrated circuit model size based upon the net invariants.
Claim 16
Dependent Claim
19 words
The system of claim 12 in which the restricting means comprises means for partitioning the tests into predetermined categories.
Claim 17
Dependent Claim
28 words
The system of claim 13 in which the providing means comprises means for providing the net invariants as constraints of the output of latches of the integrated circuit.
Claim 18
Independent Claim
99 words
A system for reducing a model size of integrated circuit model comprising: means for generating a plurality of tests for simulating the integrated circuit; means for restricting the plurality of tests based on the characteristics of the integrated circuit to provide a restricted plurality of tests; means for providing a plurality of net invariants based upon the restricted plurality of tests; means for minimizing the integrated circuit model size based upon the net invariants; means for evaluating the minimized integrated circuit model using cycle simulation wherein all gates in the minimized integrated circuit model is evaluated for each cycle.
Claim 19
Independent Claim
99 words
A system for reducing a model size of integrated circuit model comprising: means for generating a plurality of tests for simulating the integrated circuit; means for restricting the plurality of tests based on the characteristics of the integrated circuit to provide a restricted plurality of tests; means for providing a plurality of net invariants based upon the restricted plurality of tests; means for minimizing the integrated circuit model size based upon the net invariants; means for evaluating the minimized integrated circuit model using cycle simulation wherein all gates in the minimized integrated circuit model is evaluated for each cycle.
Claim 20
Dependent Claim
19 words
The system of claim 15 in which the restricting means comprises means for partitioning the tests into predetermined categories.
Claim 21
Dependent Claim
28 words
The system of claim 16 in which the providing means comprises means for providing the net invariants as constraints of the output of latches of the integrated circuit.
Claim 22
Dependent Claim
72 words
A computer readable medium containing program instructions for verifying an integrated circuit model via simulation, the program instructions for: (a) precalculating a reduced model based upon net invariants of the integrated circuit, wherein the net invariants are based upon a restricted plurality of tests based on characteristics of the integrated circuit; and (b) evaluating the reduced model using cycle simulation wherein all gates in the reduced model is evaluated for each cycle.
Claim 23
Dependent Claim
72 words
A computer readable medium containing program instructions for verifying an integrated circuit model via simulation, the program instructions for: (a) precalculating a reduced model based upon net invariants of the integrated circuit, wherein the net invariants are based upon a restricted plurality of tests based on characteristics of the integrated circuit; and (b) evaluating the reduced model using cycle simulation wherein all gates in the reduced model is evaluated for each cycle.
References Cited (Backward Citations)
US4801870A
Cited
US4763289A
Cited
US4916612A
Cited
US5053980A
Cited
US4985860A
Cited
US5163016A
Cited
US5291427A
Cited
US5462768A
Cited
US5467462A
Cited
US5392227A
Cited
US5781764A
Cited
US5452239A
Cited
US5640546A
Cited
US5446676A
Cited
US5553008A
Cited
US5446652A
Cited
US5475832A
Cited
US5384720A
Cited
US5596585A
Cited
US5784593A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |