US6049482A
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Non-volatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1998-12-21
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Granted: 2000-04-11
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Expires: 2018-12-21
Abstract
Abstract A non-volatile semiconductor memory device includes a memory cell array constituted of a plurality of memory cell units arranged on a semiconductor substrate in rows and columns, each of the memory cell units is constituted of a plurality of electrically rewritable memory cells connected to each other, and has a selective transistor at one end, and a plurality of bit lines arranged in parallel in a column direction and connected to corresponding one of the memory cell units at the one end of the memory cell unit, and a selective gate line connected to a gate of the selective transistor. In data writing operation, the voltage Vsg of the selective gate line is set at a voltage which is higher than an external power supply voltage and satisfies the relationship Vth(0)<Vsg<Vbit+Vth(-Vbit) (wherein Vth(x) is the threshold voltage of the selective transistor when a semiconductor substrate surface in which the memory cell array is formed is applied with x volt, and Vbit is a voltage applied to non-select bit lines among the plurality of bit lines). In this manner, the non-volatile semiconductor memory device sets the voltage Vbit higher than the external power supply voltage.
Inventors
- 👤 Seiichi Aritome
- 👤 Kazuhiro Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:39
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
246 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, each of the memory cell units having a first selective transistor at one end; a plurality of data lines arranged in parallel substantially in a column direction, each of the data lines being connected to corresponding memory cell units at the one end of each of the memory cell units; and a selective gate line connected to a gate of the first selective transistor, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in selected one of the memory cells constituting selected one of the memory cell units connected to selected one of the data lines, a voltage Vsg of the selective gate line is set at a certain voltage which is higher than an external power supply voltage and satisfies a relationship Vth(0)<Vsg<Vbit+Vth(-Vbit) where Vth(x) is a threshold voltage of the first selective transistor in applying x volt to a semiconductor substrate surface on which the memory cell array is formed, and Vbit is a voltage applied to a non-select data line among the plurality of data lines, and the voltage Vbit is set at a voltage higher than the external power supply voltage.
Claim 2
Dependent Claim
246 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, each of the memory cell units having a first selective transistor at one end; a plurality of data lines arranged in parallel substantially in a column direction, each of the data lines being connected to corresponding memory cell units at the one end of each of the memory cell units; and a selective gate line connected to a gate of the first selective transistor, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in selected one of the memory cells constituting selected one of the memory cell units connected to selected one of the data lines, a voltage Vsg of the selective gate line is set at a certain voltage which is higher than an external power supply voltage and satisfies a relationship Vth(0)<Vsg<Vbit+Vth(-Vbit) where Vth(x) is a threshold voltage of the first selective transistor in applying x volt to a semiconductor substrate surface on which the memory cell array is formed, and Vbit is a voltage applied to a non-select data line among the plurality of data lines, and the voltage Vbit is set at a voltage higher than the external power supply voltage.
Claim 3
Dependent Claim
26 words
The non-volatile semiconductor memory device according to claim 1, wherein each of the memory cell units has a second selective transistor at the other end thereof.
Claim 4
Dependent Claim
31 words
The non-volatile semiconductor memory device according to claim 1, wherein the memory cells constituting each of the memory cell units are connected in series to constitute a NAND type memory cell.
Claim 5
Dependent Claim
77 words
The non-volatile semiconductor memory device according to claim 1, wherein the semiconductor memory device further executes an operation during the data writing operation, in which voltages of the data lines are transferred to the memory cell units each via the first selective transistor before the voltage Vsg of the selective gate line is set at the certain voltage, by setting the voltage Vsg of the selective gate line at a high voltage higher than the certain voltage.
Claim 6
Dependent Claim
36 words
The non-volatile semiconductor memory device according to claim 4, wherein each of the memory cells has a control gate, the control gate being applied with the high voltage during a beginning of the data writing operation.
Claim 7
Dependent Claim
37 words
The non-volatile semiconductor memory device according to claim 1, wherein the voltage Vsg is high enough to transfer a voltage of the selected one of the data lines to the selected one of the memory cell units.
Claim 8
Dependent Claim
241 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, each of the memory cell units having a first selective transistor at one end; a plurality of data lines arranged in parallel substantially in a column direction, each of the data lines being connected to corresponding memory cell units at the one end of each of the memory cell units; and a selective gate line connected to a gate of the first selective transistor, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in selected one of the memory cells constituting selected one of the memory cell units connected to selected one of the data lines, a voltage Vsg of the selective gate line is set at a certain voltage which satisfies a relationship Vth(Vwell)<Vsg<Vbit+Vth(-Vbit+Vwell) where Vth(x) is a threshold voltage of the first selective transistor in applying x volt to a semiconductor substrate surface on which the memory cell array is formed, and Vbit is a voltage applied to non-select data line among the plurality of data lines, and Vwell is a voltage of the semiconductor substrate surface on which the memory cell array is formed and satisfies Vwell<0.
Claim 9
Dependent Claim
241 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, each of the memory cell units having a first selective transistor at one end; a plurality of data lines arranged in parallel substantially in a column direction, each of the data lines being connected to corresponding memory cell units at the one end of each of the memory cell units; and a selective gate line connected to a gate of the first selective transistor, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in selected one of the memory cells constituting selected one of the memory cell units connected to selected one of the data lines, a voltage Vsg of the selective gate line is set at a certain voltage which satisfies a relationship Vth(Vwell)<Vsg<Vbit+Vth(-Vbit+Vwell) where Vth(x) is a threshold voltage of the first selective transistor in applying x volt to a semiconductor substrate surface on which the memory cell array is formed, and Vbit is a voltage applied to non-select data line among the plurality of data lines, and Vwell is a voltage of the semiconductor substrate surface on which the memory cell array is formed and satisfies Vwell<0.
Claim 10
Dependent Claim
26 words
The non-volatile semiconductor memory device according to claim 7, wherein each of the memory cell units has a second selective transistor at the other end thereof.
Claim 11
Dependent Claim
31 words
The non-volatile semiconductor memory device according to claim 7, wherein the memory cells constituting each of the memory cell units are connected in series to constitute a NAND type memory cell.
Claim 12
Dependent Claim
77 words
The non-volatile semiconductor memory device according to claim 7, wherein the semiconductor memory device further executes an operation during the data writing operation, in which voltages of the data lines are transferred to the memory cell units each via the first selective transistor before the voltage Vsg of the selective gate line is set at the certain voltage, by setting the voltage Vsg of the selective gate line at a high voltage higher than the certain voltage.
Claim 13
Dependent Claim
36 words
The non-volatile semiconductor memory device according to claim 10, wherein each of the memory cells has a control gate, the control gate being applied with the high voltage during a beginning of the data writing operation.
Claim 14
Dependent Claim
37 words
The non-volatile semiconductor memory device according to claim 7, wherein the voltage Vsg is high enough to transfer a voltage of the selected one of the data lines to the selected one of the memory cell units.
Claim 15
Dependent Claim
225 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, the memory cell units having selective transistors at one ends, respectively; a plurality of bit lines arranged in parallel substantially in a column direction, each of the bit lines being connected to corresponding memory cell units at the one ends of the memory cell units; and a selective gate line connected to gates of the selective transistors, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in at least selected one of the memory cells constituting at least selected one of the memory cell units connected to at least selected one of the bit lines, a voltage Vsg of the selective gate line is set at a first voltage higher than a power supply voltage to transfer voltages of the bit lines to the memory cell units through the selective transistors, and the voltage Vsg of the selective gate line is set at a second voltage higher than the power supply voltage to cut off at least a part of the selective transistors thereafter.
Claim 16
Dependent Claim
225 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, the memory cell units having selective transistors at one ends, respectively; a plurality of bit lines arranged in parallel substantially in a column direction, each of the bit lines being connected to corresponding memory cell units at the one ends of the memory cell units; and a selective gate line connected to gates of the selective transistors, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in at least selected one of the memory cells constituting at least selected one of the memory cell units connected to at least selected one of the bit lines, a voltage Vsg of the selective gate line is set at a first voltage higher than a power supply voltage to transfer voltages of the bit lines to the memory cell units through the selective transistors, and the voltage Vsg of the selective gate line is set at a second voltage higher than the power supply voltage to cut off at least a part of the selective transistors thereafter.
Claim 17
Dependent Claim
50 words
The non-volatile semiconductor memory device according to claim 13, wherein a voltage of the semiconductor substrate surface on which the memory cell array is formed is set at a voltage lower than a ground potential when the voltage Vsg of the selective gate line is set at the second voltage.
Claim 18
Dependent Claim
29 words
The non-volatile semiconductor memory device according to claim 13, wherein a voltage of a non-write bit line among the bit lines is set higher than the power supply voltage.
Claim 19
Dependent Claim
36 words
The non-volatile semiconductor memory device according to claim 13, wherein the second voltage is high enough to transfer a voltage of the selected one of bit lines to the selected one of the memory cell units.
Claim 20
Dependent Claim
222 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, the memory cell units having selective transistors at one ends, respectively; a plurality of bit lines arranged in parallel substantially in a column direction, each of the bit lines being connected to corresponding memory cell units at the one ends of the memory cell units; and a selective gate line connected to a gate of the selective transistors, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in at least selected one of the memory cells constituting at least selected one of the memory cell units connected to at least selected one of the bit lines, after transferring voltages of the bit lines to the memory cell units through the selective transistors, a voltage of the selective gate line is set higher than a power supply voltage and a voltage of a semiconductor substrate surface on which the memory cell array is formed is set lower than a ground potential to cut off at least a part of the selective transistors.
Claim 21
Dependent Claim
222 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, the memory cell units having selective transistors at one ends, respectively; a plurality of bit lines arranged in parallel substantially in a column direction, each of the bit lines being connected to corresponding memory cell units at the one ends of the memory cell units; and a selective gate line connected to a gate of the selective transistors, the non-volatile semiconductor memory device executing an operation wherein, during data writing operation of writing data in at least selected one of the memory cells constituting at least selected one of the memory cell units connected to at least selected one of the bit lines, after transferring voltages of the bit lines to the memory cell units through the selective transistors, a voltage of the selective gate line is set higher than a power supply voltage and a voltage of a semiconductor substrate surface on which the memory cell array is formed is set lower than a ground potential to cut off at least a part of the selective transistors.
Claim 22
Dependent Claim
29 words
The non-volatile semiconductor memory device according to claim 17, wherein a voltage of a non-write bit line among the bit lines is set higher than the power supply voltage.
Claim 23
Dependent Claim
196 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, each of the memory cell units having a first selective transistor at one end; a plurality of data lines arranged in parallel substantially in a column direction, each of the data lines being connected to corresponding memory cell units at the one end of each of the memory cell units; a selective gate line connected to a gate of the first selective transistor; and a substrate potential controller for setting a voltage of the semiconductor substrate as a negative voltage, the non-volatile semiconductor memory device executing an operation wherein a select data line among the data lines is applied with a voltage insufficient for cutting off the first selective transistor, and a non-select data line among the data lines is applied with a voltage for cutting off the first selective transistor to simultaneously write a plurality of data in the memory cells.
Claim 24
Dependent Claim
196 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a memory cell array formed on the semiconductor substrate, the memory cell array comprising a plurality of memory cell units arranged in rows and columns, each of the memory cell units being constituted of a plurality of electrically rewritable memory cells connected to each other, each of the memory cell units having a first selective transistor at one end; a plurality of data lines arranged in parallel substantially in a column direction, each of the data lines being connected to corresponding memory cell units at the one end of each of the memory cell units; a selective gate line connected to a gate of the first selective transistor; and a substrate potential controller for setting a voltage of the semiconductor substrate as a negative voltage, the non-volatile semiconductor memory device executing an operation wherein a select data line among the data lines is applied with a voltage insufficient for cutting off the first selective transistor, and a non-select data line among the data lines is applied with a voltage for cutting off the first selective transistor to simultaneously write a plurality of data in the memory cells.
Claim 25
Dependent Claim
31 words
The non-volatile semiconductor memory device according to claim 19, wherein the memory cells constituting each of the memory cell units are connected in series to constitute a NAND type memory cell.
References Cited (Backward Citations)
JPH0697455A
Cited
US5877524A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |