Abstract The invention provides an integrated systolic architecture which can perform both forward and inverse Discrete Wavelet Transforms with a minimum of complexity. A plurality of processing cells, each having an adder and a multiplier, are coupled to a set of multiplexers and delay elements to selectively receive a single input datastream in the forward DWT mode and two datastreams in the inverse DWT mode. In the forward DWT mode, the integrated architecture decomposes the input datastream into two output sequences--a high frequency sub-band output and a low frequency sub-band output. In the inverse DWT mode, the integrated architecture reconstructs the original input sequence by outputting even terms and odd terms on alternating clock cycles. As a result, the architecture can achieve 100% utilization and is suitable to be implemented in VLSI circuitry.
A systolic array for computing an inverse Discrete Wavelet Transform of a high-frequency sub-band input and a low-frequency sub-band input, said array comprising: an even output generating block, said even output generating block generating even numbered outputs of said output datastream; and an odd output generating block generating odd numbered outputs of said output bitstream; a plurality of processing cells selectively coupled to said high-frequency sub-band input and said low-frequency sub-band input; each processing computing an intermediate output; an adder/controller selectively adding said intermediate outputs from said processing cells; and delay elements selectively coupled to said processing cells, said elements delaying selectively said high frequency sub-band inputs and said low-frequency sub-band inputs to compute the inverse Discrete Wavelet Transform.
Claim 2
Dependent Claim
119 words
A systolic array for computing an inverse Discrete Wavelet Transform of a high-frequency sub-band input and a low-frequency sub-band input, said array comprising: an even output generating block, said even output generating block generating even numbered outputs of said output datastream; and an odd output generating block generating odd numbered outputs of said output bitstream; a plurality of processing cells selectively coupled to said high-frequency sub-band input and said low-frequency sub-band input; each processing computing an intermediate output; an adder/controller selectively adding said intermediate outputs from said processing cells; and delay elements selectively coupled to said processing cells, said elements delaying selectively said high frequency sub-band inputs and said low-frequency sub-band inputs to compute the inverse Discrete Wavelet Transform.
Claim 3
Dependent Claim
40 words
A systolic array according to claim 1 wherein each intermediate output is a function of an inverse filter coefficient, said inverse filter coefficients selected to be symmetric to reduce the number of processing cells required to computer the inverse DWT.