Digital pulse width modulator

Claim 2

A digital pulse width modulation circuit, comprising: a first clock to provide a first pulse width signal having a fixed frequency; a second clock to provide a second pulse width signal having a second frequency proportional to said fixed frequency; means for producing a first count based on said fixed frequency and for producing a second count based on said second frequency; a counter to continually accumulate said first and second counts, and upon a predetermined final count to provide an output pulse width signal based on said final count; and means, responsive to said second count and said final count, for generating a waveform signal having a duty cycle; wherein said duty cycle is a proportion of said second count to said final count.

Claim 3

The circuit of claim 1 wherein said second clock is an analog to digital converter coupled to said first pulse width signal, and configured to provide said second pulse width signal based on a variable analog input.

Claim 4

The circuit of claim 2 wherein said converter is a voltage-to-frequency converter, and said variable analog input is a voltage signal.

Claim 5

The circuit of claim 1 wherein said producing means includes a divider coupled to said first pulse width signal, and configured to provide a square wave signal based on said first pulse width signal, said square wave signal transitioning between high and low states.

Claim 6

The circuit of claim 4 wherein said producing means further includes a circuit for summing said fixed frequency and one of said states to produce said first count, and for summing said second frequency and the other of said states to produce said second count.

Claim 7

The circuit of claim 1 wherein said generating means comprises a set/reset flip flop.

Claim 8

The circuit of claim 1 wherein said duty cycle is within a range of 50 to 75 percent.

Claim 9

The circuit of claim 3 wherein said voltage signal is between 0 and 10 volts.

Claim 10

The circuit of claim 4 wherein said divider divides said first pulse width signal by 512.

Claim 11

The circuit of claim 1 wherein said first pulse width signal is a high frequency clock signal having a frequency range of approximately 10 kHz to 1.536 MHz.

Claim 12

A digital pulse width modulation circuit, comprising: a clock to provide a first pulse width signal having a fixed frequency; a voltage to frequency converter, coupled to said first pulse width signal, and configured to provide a second pulse width signal based on a variable voltage input, said second pulse width signal having a second frequency proportional to said fixed frequency; a frequency divider, coupled to said first pulse width signal and configured to provide a square wave signal having a period proportional to said first pulse width signal, said square wave signal transitioning between high and low states; a circuit for producing a first count signal based on said fixed frequency and one of said states, and for producing a second count signal based on said second frequency and the other of said states; a counter that accumulates said first and second count signals until a predetermined final count is achieved, wherein said counter generates a final count signal; and a flip-flop, responsive to said second count signal and said final count signal, for providing a waveform signal having a duty cycle as a proportion of said second count signal to said final count signal.

Claim 13

A digital pulse width modulation circuit, comprising: a clock to provide a first pulse width signal having a fixed frequency; a voltage to frequency converter, coupled to said first pulse width signal, and configured to provide a second pulse width signal based on a variable voltage input, said second pulse width signal having a second frequency proportional to said fixed frequency; a frequency divider, coupled to said first pulse width signal and configured to provide a square wave signal having a period proportional to said first pulse width signal, said square wave signal transitioning between high and low states; a circuit for producing a first count signal based on said fixed frequency and one of said states, and for producing a second count signal based on said second frequency and the other of said states; a counter that accumulates said first and second count signals until a predetermined final count is achieved, wherein said counter generates a final count signal; and a flip-flop, responsive to said second count signal and said final count signal, for providing a waveform signal having a duty cycle as a proportion of said second count signal to said final count signal.

Claim 16

The method of claim 12 wherein said duty cycle is within a range of 50 to 75 percent.

Claim 17

The method of claim 12 wherein said producing step further comprises the steps of: dividing said first pulse width signal by a fixed count; generating a square wave signal having a period proportional to said first pulse width signal, said square wave signal transitioning between high and low states; and producing said first count signal based on said fixed frequency and one of said states, and said second count signal based on said second frequency and the other of said states.

Claim 18

The method of claim 12 wherein said variable analog input is a voltage between a range of 0 to 10 volts.