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US6038020A
Expired / Lapsed
US
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Mask pattern verification apparatus employing super-resolution technique, mask pattern verification method employing super-resolution technique, and medium with program thereof
Assignee: Renesas Electronics Corp
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Filing: 1998-09-22
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Granted: 2000-03-14
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Expires: 2018-09-22
Abstract
Abstract A mask pattern verification apparatus includes a semiconductor circuit layout unit for generating layout data from semiconductor circuit data, a super-resolution corresponding pattern verification unit for verifying a pattern of the layout data generated by the semiconductor circuit layout unit according to a pitch with a line width and a space width, an optical simulation unit carrying out optical simulation on an error site of a pitch detected by the super-resolution corresponding pattern verification unit to output light intensity, and a contour output unit for generating and providing a contour according to the light intensity output from the optical simulation unit.
Inventors
- 👤 Eiji Tsukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:22
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398; G01; G01N; G01N21/00; G01N21/84; G01N21/88; G01N21/95; G01N21/956; G01N21/95607; G03; G03F; G03F1/00; G03F1/36; G03F1/68; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; G03F7/70441; H; H01; H01J; H01J37/00; H01J37/30; H01J37/317; H01J37/3174
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
71 words
A mask pattern verification method comprising the steps of: generating layout data from semiconductor circuit data; detecting an error site of a pitch of a pattern of said generated layout data according to a pitch including a line width and a space width; carrying out optical simulation of said detected error site of a pitch to output light intensity; and generating and providing a contour according to said output light intensity.
Claim 2
Dependent Claim
71 words
A mask pattern verification method comprising the steps of: generating layout data from semiconductor circuit data; detecting an error site of a pitch of a pattern of said generated layout data according to a pitch including a line width and a space width; carrying out optical simulation of said detected error site of a pitch to output light intensity; and generating and providing a contour according to said output light intensity.
Claim 3
Dependent Claim
64 words
A mask pattern verification method comprising the steps of: generating layout data from semiconductor circuit data; detecting an error site of a hole of said generated layout data from a position relationship with an adjacent pattern; carrying out optical simulation on said detected error site of a hole to output light intensity; and generating and providing a contour according to said output light intensity.
Claim 4
Dependent Claim
64 words
A mask pattern verification method comprising the steps of: generating layout data from semiconductor circuit data; detecting an error site of a hole of said generated layout data from a position relationship with an adjacent pattern; carrying out optical simulation on said detected error site of a hole to output light intensity; and generating and providing a contour according to said output light intensity.
Claim 5
Dependent Claim
63 words
A mask pattern verification method comprising the steps of: generating layout data from semiconductor circuit data; carrying out optical simulation on said generated layout data to output light intensity; generating and providing a contour according to said output light intensity; verifying a distortion of said output contour according to said generated layout data; and correcting said layout data according to said verification result.
Claim 6
Dependent Claim
63 words
A mask pattern verification method comprising the steps of: generating layout data from semiconductor circuit data; carrying out optical simulation on said generated layout data to output light intensity; generating and providing a contour according to said output light intensity; verifying a distortion of said output contour according to said generated layout data; and correcting said layout data according to said verification result.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-14 | 2003-09-13 | 2004-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-14 | 2007-09-13 | 2008-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-14 | 2011-09-13 | 2012-03-14 | $7700.00 | Window Closed / Lapsed |