← Back to Patent Explorer
US6028652A Expired / Lapsed US ⏱️ 0.0 years remaining

Array substrate for display device and manufacturing method thereof

Assignee: Japan Display Central Inc
•
Filing: 1998-11-06
•
Granted: 2000-02-22
•
Expires: 2018-11-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127). With such an arrangement, an appropriate storage capacitor can be formed by causing the scanning lines and pixel electrode to overlap each other without having to decrease the manufacturing yield while enabling achievement of high aperture ratio.

Inventors

  • 👤 Masayuki Dohjo
  • 👤 Hideo Kawano
  • 👤 Akira Kubo
  • 👤 Makoto Shibusawa
  • 👤 Tetsuya Iizuka
  • 👤 Tamio Nakai
  • 👤 Kazushige Mori

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 19:36
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/12; H04N9/31; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13452; G02F1/13458; G02F1/136; G02F1/1362; G02F1/136213; G02F1/136227; H10; H10D; H10D86/00; H10D86/40; H10D86/441; H10D86/60; G02F1/136286; G02F1/13629

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 238 words
A method of manufacturing an array substrate for a display device including a plurality of scanning lines on a substrate, thin film transistors each having a first insulator film on a corresponding one of said lines, a semiconductor film thereon, a channel protective film on said semiconductor film, and source and drain electrodes electrically connected to said semiconductor film, a plurality of signal lines as each being taken out of the respective drain electrode to extend substantially perpendicularly to said scanning lines, and pixel electrodes each being electrically connected to the respective source electrode, said method comprising the steps of: forming a first wiring line layer including said scanning lines on said substrate; depositing said first insulator film and a semiconductor coated film; depositing a metal thin film on said semiconductor coated film; patterning a multi-layer film comprising at least said metal thin film and said semiconductor layer for said semiconductor film using a mask, thereby forming a second wiring line layer which includes said signal lines, said source electrodes and said drain electrodes and further forming said semiconductor film; depositing a second insulator film and forming first contact holes in said second insulator film corresponding to each said source electrode; and forming said pixel electrodes each being electrically connected to said respective source electrode through respective ones of said contact holes and overlapping at least one of said scanning lines with the first and second insulator films.
Claim 2
Independent Claim 238 words
A method of manufacturing an array substrate for a display device including a plurality of scanning lines on a substrate, thin film transistors each having a first insulator film on a corresponding one of said lines, a semiconductor film thereon, a channel protective film on said semiconductor film, and source and drain electrodes electrically connected to said semiconductor film, a plurality of signal lines as each being taken out of the respective drain electrode to extend substantially perpendicularly to said scanning lines, and pixel electrodes each being electrically connected to the respective source electrode, said method comprising the steps of: forming a first wiring line layer including said scanning lines on said substrate; depositing said first insulator film and a semiconductor coated film; depositing a metal thin film on said semiconductor coated film; patterning a multi-layer film comprising at least said metal thin film and said semiconductor layer for said semiconductor film using a mask, thereby forming a second wiring line layer which includes said signal lines, said source electrodes and said drain electrodes and further forming said semiconductor film; depositing a second insulator film and forming first contact holes in said second insulator film corresponding to each said source electrode; and forming said pixel electrodes each being electrically connected to said respective source electrode through respective ones of said contact holes and overlapping at least one of said scanning lines with the first and second insulator films.
Claim 3
Dependent Claim 51 words
The method according to claim 1, wherein each of said pixel electrodes interposed between two consecutive scanning lines overlaps one of said two consecutive scanning lines and is electrically connected to a respective one of the thin film transistors, which is associated with another one of said two consecutive scanning lines.
Claim 4
Dependent Claim 19 words
The method according to claim 1, wherein said wiring layer includes an Al layer or an Al alloy layer.
Claim 5
Dependent Claim 18 words
The method according to claim 1, wherein said patterning of a multi-layer film is performed by dry etching.
Claim 6
Dependent Claim 15 words
The method according to claim 1, wherein said semiconductor coated film is formed of a-Si:H.
Claim 7
Dependent Claim 42 words
The method according to claim 1, wherein second contact holes for exposing outer periphery portions of said signal lines and third contact holes for exposing outer periphery portions of said scanning lines are formed simultaneously with formation of said first contact holes.
Claim 8
Dependent Claim 37 words
The method according to claim 6, wherein covering layers disposed at said second and third contact holes so as to be connected with said signal and scanning lines respectively formed simultaneously with said pixel electrodes forming step.
Claim 9
Independent Claim 307 words
A method of manufacturing an array substrate for a display device including a plurality of scanning lines on a substrate, thin film transistors each having a first insulator film on a corresponding one of said lines, a semiconductor film thereon, a channel protective film on said semiconductor film, and source electrodes and drain electrodes electrically connected to said semiconductor film, a plurality of signal lines as each being taken out of the respective drain electrode to extend substantially perpendicularly to said scanning lines, and pixel electrodes each being electrically connected to the respective source electrode comprising: a first step of forming said scanning lines; a second step of depositing said first insulator film and a semiconductor coated film; a third step of depositing a metal thin film on said semiconductor coated film and patterning a multi-layer film comprising at least said metal thin film and said semiconductor film using a mask, thereby forming a second wiring line layer which includes said signal lines, said source electrodes and said drain electrodes and forming said semiconductor film; a fourth step of depositing a second insulator film and forming first contact holes in said second insulator film corresponding to said source electrode; and a fifth step of forming said pixel electrodes each being electrically coupled through a respective one of said contact holes to said respective source electrode and overlapping another scanning line with the first and second insulator films, said method further comprising the steps of: depositing said first insulator film and said semiconductor coated film simultaneously with said second step; forming light shield layers by patterning said multi-layer film using said mask simultaneously with said third step, said light shielding layers overlapping said scanning lines via said first insulator film; and forming said pixel electrode so as to overlap said light shield layers via said second insulator film.
Claim 10
Independent Claim 307 words
A method of manufacturing an array substrate for a display device including a plurality of scanning lines on a substrate, thin film transistors each having a first insulator film on a corresponding one of said lines, a semiconductor film thereon, a channel protective film on said semiconductor film, and source electrodes and drain electrodes electrically connected to said semiconductor film, a plurality of signal lines as each being taken out of the respective drain electrode to extend substantially perpendicularly to said scanning lines, and pixel electrodes each being electrically connected to the respective source electrode comprising: a first step of forming said scanning lines; a second step of depositing said first insulator film and a semiconductor coated film; a third step of depositing a metal thin film on said semiconductor coated film and patterning a multi-layer film comprising at least said metal thin film and said semiconductor film using a mask, thereby forming a second wiring line layer which includes said signal lines, said source electrodes and said drain electrodes and forming said semiconductor film; a fourth step of depositing a second insulator film and forming first contact holes in said second insulator film corresponding to said source electrode; and a fifth step of forming said pixel electrodes each being electrically coupled through a respective one of said contact holes to said respective source electrode and overlapping another scanning line with the first and second insulator films, said method further comprising the steps of: depositing said first insulator film and said semiconductor coated film simultaneously with said second step; forming light shield layers by patterning said multi-layer film using said mask simultaneously with said third step, said light shielding layers overlapping said scanning lines via said first insulator film; and forming said pixel electrode so as to overlap said light shield layers via said second insulator film.
Claim 11
Dependent Claim 18 words
The method according to claim 1, wherein said first and second insulator films include a silicone nitride film.
Claim 12
Dependent Claim 25 words
The method according to claim 9, wherein said first insulator film includes a silicone oxide film disposed between said substrate and said silicone nitride film.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-02-21 2003-08-23 2004-02-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-02-21 2007-08-23 2008-02-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-02-21 2011-08-23 2012-02-22 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag