US6013537A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of semiconductor wafer testing
Assignee: International Business Machines Corp
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Filing: 1998-03-10
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Granted: 2000-01-11
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Expires: 2018-03-10
Abstract
Abstract The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the devices perform characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.
Inventors
- 👤 Daniel M. Kuchta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:09
CPC Classifications
H; H01; H01S; H01S5/00; H01S5/02; H01S5/026; H01S5/0261; G; G01; G01R; G01R31/00; G01R31/28; G01R31/282; G01R31/2822; G01R31/2831; G01R31/2851; G01R31/2884; H01S5/0014; H01S5/0042; G01R31/316; H01S5/0201; H01S5/04; H01S5/042; H01S5/0421; H01S5/0422; H01S5/0428; H01S5/10; H01S5/18; H01S5/183
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
163 words
A method comprising the steps of: providing a wafer; forming an electrical device within said wafer; said electrical device having: a top layer forming an upper device surface, said top layer having a first top surface and a second top surface; a first electrode making contact with said first top surface; a first device contact making electrical contact with said first electrode; a bottom layer forming a lower device surface, said bottom layer having a first bottom surface and a second bottom surface, said first bottom surface being attached to said second top surface; a second electrode making contact with said first bottom surface; a substrate attached to said second bottom surface; a second device contact making electrical contact with said substrate; attaching a conductive plate to a portion of said first top surface; forming a third device contact in electrical contact with said conductive plate; and forming a semi-insulated region in said top layer between said portion and said first bottom surface.
Claim 2
Independent Claim
163 words
A method comprising the steps of: providing a wafer; forming an electrical device within said wafer; said electrical device having: a top layer forming an upper device surface, said top layer having a first top surface and a second top surface; a first electrode making contact with said first top surface; a first device contact making electrical contact with said first electrode; a bottom layer forming a lower device surface, said bottom layer having a first bottom surface and a second bottom surface, said first bottom surface being attached to said second top surface; a second electrode making contact with said first bottom surface; a substrate attached to said second bottom surface; a second device contact making electrical contact with said substrate; attaching a conductive plate to a portion of said first top surface; forming a third device contact in electrical contact with said conductive plate; and forming a semi-insulated region in said top layer between said portion and said first bottom surface.
Claim 3
Dependent Claim
84 words
The method of claim 1 in which said electrical device is capable of producing an output having characteristics and further comprising the steps of: providing an AC source connected across said first device contact and said third device contact; providing a DC source connected across said first device contact and said second device contact; providing means for measuring said characteristics responsive to said AC and said DC sources wherein said means for measuring makes electrical contact with at least one of said device contacts.
Claim 4
Dependent Claim
18 words
A method as in claim 1 in which said electrical device is a vertical cavity surface emitting laser.
Claim 5
Dependent Claim
40 words
A method as in claim 1 wherein: said first device contact forms the AC/DC port of a bias-tee; said second device contact forms the DC-only port of said bias-tee; said third device contact forms the AC-only port of said bias-tee.
References Cited (Backward Citations)
US5317587A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |