US6011433A
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Generalized procedure for the calibration of switched capacitor gain stages
Assignee: Microsemi Storage Solutions Ltd
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Filing: 1998-10-22
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Granted: 2000-01-04
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Expires: 2018-10-22
Abstract
Abstract Within the field of integrated circuits used in amplifiers, a structure and improved method for calibrating a switched capacitor gain stage wherein the time required to self-calibrate a switched capacitor gain stage and the associated structure are reduced. The invention utilizes only a single calibration step which is performed while the output of the amplifier being calibrated is monitored. Instead of utilizing a plurality of capacitors C a1 --C an each in parallel with groups of trim capacitors C T , a single capacitor C a is used and connected to switches S 1a1 and S 1b1 . Further, instead of a group of trim capacitors C T being connected in parallel with the capacitor to be trimmed, each of plurality of trim capacitors C T1 -C TN is connected between the input to the operational amplifier and a respective corresponding switch S 1a2 -S 1aN to the input reference voltage node V b0 . As well, switches S 1b2 -S 1bn connect the respective junctions between the trim capacitors C T1 -C TN to ground.
Inventors
- 👤 David Graham Nairn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:51
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/005
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
356 words
A method of calibrating a switched capacitor gain stage comprising: (a) applying reference voltages to a gain stage comprising (i) an operational amplifier having a non-inverting input connected to ground (ii) an output node Z of the operational amplifier connected via a switch S 3 to an inverting input of the operational amplifier, (iii) a capacitor C b connected from the inverting input via a switch S 2a to one of the reference voltages V b1 and via a switch S 2b to another of the reference voltages V b2 , (iv) an input capacitor C a connected from the inverting input, via a switch S 1a1 to another of the reference voltages V b0 , (v) a switch S 1b1 connected between the junction of switch S 1a1 and capacitor C a and ground, (vi) a plurality of trim capacitors, each connected from the inverting input, via respective switches S 1a2 . . . S 1an to the reference voltage V b0 , and (vii) a plurality of switches S 1b2 . . . S 1bn connected between the junction of a respective corresponding switch s 1a2 . . . S 1an and ground, (b) closing switches, S 3 , S 1a1 , S 1a2 . . . S 1an and S 2a , (c) opening switch S 3 , (d) opening switch S 2a and closing switch S 2b , (e) opening switch S 1a1 and closing switch S 1b1 , (f) opening successive ones of switches S 1a2 . . . S 1an and closing corresponding successive ones of switches S 1b2 . . . S 1bn until either: (I) a voltage at the inverting input of the operational amplifier is 0, or (II) a voltage at the output of the operational amplifier is equal to a desired gain of the switched capacitor gain stage multiplied by the reference voltage V b0 , wherein: the desired gain of the switched capacitor gain stage=(V b2 -V b1 )/V b0 , and the capacitance C a is smaller than the desired gain of the switched capacitor gain stage multiplied by the capacitance C b .
Claim 2
Independent Claim
356 words
A method of calibrating a switched capacitor gain stage comprising: (a) applying reference voltages to a gain stage comprising (i) an operational amplifier having a non-inverting input connected to ground (ii) an output node Z of the operational amplifier connected via a switch S 3 to an inverting input of the operational amplifier, (iii) a capacitor C b connected from the inverting input via a switch S 2a to one of the reference voltages V b1 and via a switch S 2b to another of the reference voltages V b2 , (iv) an input capacitor C a connected from the inverting input, via a switch S 1a1 to another of the reference voltages V b0 , (v) a switch S 1b1 connected between the junction of switch S 1a1 and capacitor C a and ground, (vi) a plurality of trim capacitors, each connected from the inverting input, via respective switches S 1a2 . . . S 1an to the reference voltage V b0 , and (vii) a plurality of switches S 1b2 . . . S 1bn connected between the junction of a respective corresponding switch s 1a2 . . . S 1an and ground, (b) closing switches, S 3 , S 1a1 , S 1a2 . . . S 1an and S 2a , (c) opening switch S 3 , (d) opening switch S 2a and closing switch S 2b , (e) opening switch S 1a1 and closing switch S 1b1 , (f) opening successive ones of switches S 1a2 . . . S 1an and closing corresponding successive ones of switches S 1b2 . . . S 1bn until either: (I) a voltage at the inverting input of the operational amplifier is 0, or (II) a voltage at the output of the operational amplifier is equal to a desired gain of the switched capacitor gain stage multiplied by the reference voltage V b0 , wherein: the desired gain of the switched capacitor gain stage=(V b2 -V b1 )/V b0 , and the capacitance C a is smaller than the desired gain of the switched capacitor gain stage multiplied by the capacitance C b .
Claim 3
Dependent Claim
189 words
A switched capacitor gain stage comprising: (i) an operational amplifier having a non-inverting input connected to ground (ii) an output node V 0 of the operational amplifier connected via a switch S 3 to an inverting input of the operational amplifier, (iii) a capacitor C b connected from the inverting input via a switch S 2a to a node for applying reference voltage V b1 and via a switch S 2b to a node for applying another reference voltage V b2 , (iv) an input capacitor C a connected from the inverting input, via a switch S 1a1 to a node for applying another reference voltage V b0 , (v) a switch S 1b1 connected between the junction of switch S1a1 and capacitor C a and ground, (vi) a plurality of trim capacitors, each connected from the inverting input, via respective switches S 1a2 . . . S 1an to the reference node V b0 , and (vii) a plurality of switches S 1b2 -S 1bn . . . s 1an connected between the junction of a respective corresponding switch s 1a2 . . . S 1an and ground.
Claim 4
Dependent Claim
189 words
A switched capacitor gain stage comprising: (i) an operational amplifier having a non-inverting input connected to ground (ii) an output node V 0 of the operational amplifier connected via a switch S 3 to an inverting input of the operational amplifier, (iii) a capacitor C b connected from the inverting input via a switch S 2a to a node for applying reference voltage V b1 and via a switch S 2b to a node for applying another reference voltage V b2 , (iv) an input capacitor C a connected from the inverting input, via a switch S 1a1 to a node for applying another reference voltage V b0 , (v) a switch S 1b1 connected between the junction of switch S1a1 and capacitor C a and ground, (vi) a plurality of trim capacitors, each connected from the inverting input, via respective switches S 1a2 . . . S 1an to the reference node V b0 , and (vii) a plurality of switches S 1b2 -S 1bn . . . s 1an connected between the junction of a respective corresponding switch s 1a2 . . . S 1an and ground.
Claim 5
Dependent Claim
174 words
A switched capacitor gain stage as defined in claim 2, including a logic circuit for: (a) closing switches S 3 , S 1a1 , S 1a2 . . . S 1an and S 2a , (b) opening switch S 3 , (c) opening switch S 2a and closing switch S 2b , (d) opening switch S 1a1 and closing switch S 1b1 , (e) opening successive ones of switches S 1a2 . . . S 1an and closing corresponding successive ones of switches S 1b2 . . . S 1bn until either: (I) a voltage at the inverting input of the operational amplifier is 9, or (II) a voltage at the output of the operational amplifier is equal to a desired gain of the switched capacitor gain stage multiplied by the reference voltage V b0 , wherein: the desired gain of the switched capacitor stage=(V b2 -V b1 )/V b0 , and the capacitance Ca is smaller than the desired gain of the switched capacitor gain stage multiplied by the capacitance C b .
Claim 6
Dependent Claim
18 words
A switched capacitor gain stage as defined in claim 3, in which the logic circuit is a processor.
Claim 7
Independent Claim
312 words
A method of calibrating a switched capacitor gain stage comprising: (a) applying reference voltages to a differential gain stage comprising: (i) a differential amplifier having a pair of inputs and a pair of output nodes, (ii) each respective output node being connected via a corresponding respective switch S 3 to a corresponding inverting input and a corresponding non-inverting input, (iii) a pair of capacitors C b respectively connected from a corresponding input via a corresponding switch S 2a to a corresponding reference voltage b 2 and V b3 , and via a corresponding switch S 2b to the corresponding voltage V b3 and V b2 respectively, (iv) a pair of input capacitors Ca connected from respective inputs, via a pair of corresponding switches S 1a to respective voltages V b1 and V bo , (v) a pair of switches S 1b1 respectively connected between the junctions of switches S 1a1 and capacitors C a to a common junction node, and (vi) two groups of trim capacitors, one terminal of each trim capacitor in each respective group connected from a respective input to the differential amplifier, via a corresponding switch s 1a2 . . . S 1an to the respective voltages V b1 and V bo , (b) closing switches S 3 , S 1a1 , S 1a2 . . . S 1an and S 2a , (c) opening switches S 3 , (d) opening switches, S 2a and closing switches S 2b , (e) opening switches S 1a1 and closing switches S 1b1 , (f) opening successive ones of switches S 1a2 . . . S 1an and closing corresponding successive ones of switches S 1b2 . . . S 1bn until either: (I) a voltage across the outputs of the operational amplifier is 0, or (II) a voltage across the outputs of the operational amplifier is V b3 -V b2 .
Claim 8
Independent Claim
312 words
A method of calibrating a switched capacitor gain stage comprising: (a) applying reference voltages to a differential gain stage comprising: (i) a differential amplifier having a pair of inputs and a pair of output nodes, (ii) each respective output node being connected via a corresponding respective switch S 3 to a corresponding inverting input and a corresponding non-inverting input, (iii) a pair of capacitors C b respectively connected from a corresponding input via a corresponding switch S 2a to a corresponding reference voltage b 2 and V b3 , and via a corresponding switch S 2b to the corresponding voltage V b3 and V b2 respectively, (iv) a pair of input capacitors Ca connected from respective inputs, via a pair of corresponding switches S 1a to respective voltages V b1 and V bo , (v) a pair of switches S 1b1 respectively connected between the junctions of switches S 1a1 and capacitors C a to a common junction node, and (vi) two groups of trim capacitors, one terminal of each trim capacitor in each respective group connected from a respective input to the differential amplifier, via a corresponding switch s 1a2 . . . S 1an to the respective voltages V b1 and V bo , (b) closing switches S 3 , S 1a1 , S 1a2 . . . S 1an and S 2a , (c) opening switches S 3 , (d) opening switches, S 2a and closing switches S 2b , (e) opening switches S 1a1 and closing switches S 1b1 , (f) opening successive ones of switches S 1a2 . . . S 1an and closing corresponding successive ones of switches S 1b2 . . . S 1bn until either: (I) a voltage across the outputs of the operational amplifier is 0, or (II) a voltage across the outputs of the operational amplifier is V b3 -V b2 .
Claim 9
Dependent Claim
206 words
A switched capacitor gain stage comprising: (i) a differential amplifier having a pair of inputs and a pair of output nodes, (ii) each respective output node being connected via a corresponding respective switch S 3 to a corresponding inverting input and a corresponding non-inverting input, (iii) a pair of capacitors C b respectively connected from a corresponding input via a corresponding switch S 2a to a reference node for applying corresponding reference voltages B b2 and V b3 , and via a corresponding switch S 2b to the node for applying corresponding voltages V b3 and V b2 respectively, (iv) a pair of input capacitors C a connected from respective inputs, via a pair of corresponding switches S 1a to nodes for applying respective voltages V b1 and V bo , (v) a pair of switches S 1b1 respectively connected between the junctions of switches S 1a1 and capacitors C a to a common junction node, and (vi) two groups of trim capacitors, one terminal of each trim capacitor in each respective group connected from a respective input to the differential amplifier, via a corresponding switch S 1a2 . . . S 1an to the nodes for applying respective voltages V b1 and V bo .
Claim 10
Dependent Claim
206 words
A switched capacitor gain stage comprising: (i) a differential amplifier having a pair of inputs and a pair of output nodes, (ii) each respective output node being connected via a corresponding respective switch S 3 to a corresponding inverting input and a corresponding non-inverting input, (iii) a pair of capacitors C b respectively connected from a corresponding input via a corresponding switch S 2a to a reference node for applying corresponding reference voltages B b2 and V b3 , and via a corresponding switch S 2b to the node for applying corresponding voltages V b3 and V b2 respectively, (iv) a pair of input capacitors C a connected from respective inputs, via a pair of corresponding switches S 1a to nodes for applying respective voltages V b1 and V bo , (v) a pair of switches S 1b1 respectively connected between the junctions of switches S 1a1 and capacitors C a to a common junction node, and (vi) two groups of trim capacitors, one terminal of each trim capacitor in each respective group connected from a respective input to the differential amplifier, via a corresponding switch S 1a2 . . . S 1an to the nodes for applying respective voltages V b1 and V bo .
Claim 11
Dependent Claim
121 words
A switched capacitor gain stage as defined in claim 6 including a logic circuit for (a) closing switches S 3 , S 1a1 , S 1a2 . . . S 1an and S 2a , (b) opening switches S 3 , (c) opening switches S 2a and closing switches S 2b , (d) opening switches S 1a1 and closing switches S 1b1 , (e) opening successive ones of switches S 1a2 . . . S 1an and closing corresponding successive ones of switches S 1b2 . . . S 1bn until either: (I) a voltage across the outputs of the operational amplifier is 0, or (II) a voltage across the outputs of the operational amplifier is V b3 -V b2 .
Claim 12
Dependent Claim
18 words
A switched capacitor gain stage as defined in claim 7, in which the logic circuit is a processor.
References Cited (Backward Citations)
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