US6007669A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Layer to layer interconnect
Assignee: Delphi Technologies Inc
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Filing: 1998-01-07
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Granted: 1999-12-28
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Expires: 2018-01-07
Abstract
Abstract The present invention includes stack flexible circuit layers having raised features or bumps for Z-axis interconnection to another circuit layer or electrical component. An intermediate or adhesive layer separates each circuit layer. The multiple layers are stacked with the raised features from one layer aligning with pads of an overlying or underlying layer and are laminated so that the raised features pierce the intermediate or adhesive layer and make electrical contact with the corresponding pad of the adjacent circuit layer. The raised features may have a shape sufficient to penetrate the intermediate and/or the adhesive layer allowing blind vias to be made without pre-drilling the intermediate or adhesive layers. The intermediate layer of film can have a function other than or in addition to that of an adhesive. For example, in a connector application where the raised feature is used to make contact to corresponding pads, a film that has a low permeability to water could be placed between the raised features and corresponding pads on the next layer. The low water permeability film would act as a sealant to prevent environmental attack on the connection. The raised feature would penetrate the sealant to make electrical contact to a corresponding pad. This would allow the connector to be disassembled and reconnected.
Inventors
- 👤 William R. Crumly
- 👤 Haim Feigenbaum
- 👤 Eric Dean Jensen
- 👤 Pete Henry Hudson
- 👤 John De Nuto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:38
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4611; H05K3/4614; H05K3/4617; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W90/00; H10W90/401; H10W90/701; H05K2201/00; H05K2201/01; H05K2201/0183; H05K2201/0195; H05K2203/00; H05K2203/11; H05K2203/1189; H05K3/10; H05K3/20; H05K3/205; H05K3/4644; H05K3/4647; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/4913; Y10T29/49139
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
158 words
A method of making a multi-layer electrical interconnect system comprising: providing a first circuit layer having a first set of electrically conductive traces with raised features on a first dielectric layer, and a first adhesive layer overlying the first circuit layer including the raised features, placing a second dielectric layer having holes formed therein over the first circuit so that the holes are aligned with the raised features, said second dielectric layer having a second set of electrically conductive traces formed on a top surface overlying the holes in the second dielectric layer and the raised features in the first circuit layer, wherein said adhesive layer does not have a hole formed therethrough at a location over any of the raised features, and bonding the layers together so that a raised feature of the first circuit layer penetrates the adhesive layer and provides an electrical contact with one of the electrically conductive traces on the second dielectric layer.
Claim 2
Independent Claim
158 words
A method of making a multi-layer electrical interconnect system comprising: providing a first circuit layer having a first set of electrically conductive traces with raised features on a first dielectric layer, and a first adhesive layer overlying the first circuit layer including the raised features, placing a second dielectric layer having holes formed therein over the first circuit so that the holes are aligned with the raised features, said second dielectric layer having a second set of electrically conductive traces formed on a top surface overlying the holes in the second dielectric layer and the raised features in the first circuit layer, wherein said adhesive layer does not have a hole formed therethrough at a location over any of the raised features, and bonding the layers together so that a raised feature of the first circuit layer penetrates the adhesive layer and provides an electrical contact with one of the electrically conductive traces on the second dielectric layer.
Claim 3
Dependent Claim
49 words
A method as set forth in claim 1 wherein said second dielectric layer includes a solder dot received in one of said holes in the second dielectric layer for soldering a raised feature on the first circuit to one of the electrically conductive traces on the second dielectric layer.
Claim 4
Dependent Claim
34 words
A method as set forth in claim 1 further comprising the step of placing a layer of silicone gel over the adhesive layer prior to placing the second dielectric layer on said first circuit.
Claim 5
Dependent Claim
33 words
A method as set forth in claim 1 further comprising the steps of placing silicone gel into one of the holes formed in the second dialectric layer prior to laminating the layers together.
Claim 6
Dependent Claim
15 words
A method as set forth in claim 1 wherein the first dielectric layer is flexible.
Claim 7
Dependent Claim
15 words
A method as set forth in claim 1 wherein the second dielectric layer is flexible.
Claim 8
Independent Claim
90 words
A method of making an electrical interconnection system comprising: providing a first circuit layer having electrical conductive trace with a raised contact feature; providing an intermediate layer over the first circuit layer that does not have a hole formed therethrough at a location over the raised feature; providing an electrical component over the intermediate layer and having a contact pad aligned with the raised feature; and laminating the layers to the component so that the raised contact feature penetrates the intermediate layer and makes electrical connection to the contact pad.
Claim 9
Independent Claim
90 words
A method of making an electrical interconnection system comprising: providing a first circuit layer having electrical conductive trace with a raised contact feature; providing an intermediate layer over the first circuit layer that does not have a hole formed therethrough at a location over the raised feature; providing an electrical component over the intermediate layer and having a contact pad aligned with the raised feature; and laminating the layers to the component so that the raised contact feature penetrates the intermediate layer and makes electrical connection to the contact pad.
Claim 10
Dependent Claim
16 words
A method as set forth in claim 7 wherein the component comprises an integrated circuit chip.
Claim 11
Dependent Claim
16 words
A method as set forth in claim 7 wherein the intermediate layer comprises an adhesive layer.
Claim 12
Dependent Claim
17 words
A method as set forth in claim 7 wherein the circuit layer is a flexible circuit layer.
Claim 13
Dependent Claim
22 words
A method as set forth in claim 1 wherein the adhesive layer is one of a solid sheet, paste, gel or liquid.
Claim 14
Dependent Claim
22 words
A method as set forth in claim 7 wherein the intermediate layer is one of a solid sheet, paste, gel or liquid.
Claim 15
Independent Claim
309 words
A method of making a multi-layer electrical interconnect system comprising: providing a first circuit layer having a first set of electrically conductive traces with raised features on a first dielectric layer, and a first adhesive layer overlying the first circuit layer including the raised features, placing a second dielectric layer having holes formed therein over the first circuit so that the holes are aligned with the raised features, said second dielectric layer having a second set of electrically conductive traces formed on a top surface overlying the holes in the second dielectric layer and the raised features in the first circuit layer, wherein said adhesive layer does not have a hole formed therethrough at a location over any of the raised features, bonding the layers together so that a raised feature of the first circuit layer penetrates the adhesive layer and provides an electrical contact with one of the electrically conductive traces on the second dielectric layer, providing a second adhesive layer over lying the second set of electrical conductive traces including raised portions of the second set of electrically conductive traces, placing a third dielectric layer having holes formed therein over the second set of traces so that the holes are aligned with the raised features on the second set of traces, said third dielectric layer having a third set of electrically conductive traces formed on a top surface overlying the holes in the third dielectric layer and the second set of traces having raised features, and wherein the second adhesive layer does not have a hole formed therethrough at a location over the raised features on the second traces, and bonding the layers together so that a raised features of the second set of traces penetrates the second adhesive layer and provides an electrical contact with one of the electrically conductive traces on the third dielectric layer.
Claim 16
Independent Claim
309 words
A method of making a multi-layer electrical interconnect system comprising: providing a first circuit layer having a first set of electrically conductive traces with raised features on a first dielectric layer, and a first adhesive layer overlying the first circuit layer including the raised features, placing a second dielectric layer having holes formed therein over the first circuit so that the holes are aligned with the raised features, said second dielectric layer having a second set of electrically conductive traces formed on a top surface overlying the holes in the second dielectric layer and the raised features in the first circuit layer, wherein said adhesive layer does not have a hole formed therethrough at a location over any of the raised features, bonding the layers together so that a raised feature of the first circuit layer penetrates the adhesive layer and provides an electrical contact with one of the electrically conductive traces on the second dielectric layer, providing a second adhesive layer over lying the second set of electrical conductive traces including raised portions of the second set of electrically conductive traces, placing a third dielectric layer having holes formed therein over the second set of traces so that the holes are aligned with the raised features on the second set of traces, said third dielectric layer having a third set of electrically conductive traces formed on a top surface overlying the holes in the third dielectric layer and the second set of traces having raised features, and wherein the second adhesive layer does not have a hole formed therethrough at a location over the raised features on the second traces, and bonding the layers together so that a raised features of the second set of traces penetrates the second adhesive layer and provides an electrical contact with one of the electrically conductive traces on the third dielectric layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |