US6006008A
Expired / Lapsed
US
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Motor drive system controlled by a phase accumulator and method therefor
Assignee: Lexmark International Inc
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Filing: 1997-05-29
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Granted: 1999-12-21
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Expires: 2017-05-29
Abstract
Abstract A high resolution speed control for a DC or BLDC phase-locked-loop (PLL) motor is provided. A phase accumulator sends a time varying frequency reference to the PLL input, where the average frequency sets the motor speed with a high degree of accuracy. A post divider is used to reduce the number of circuits required to implement the function.
Inventors
- 👤 David Kurt Klaffenbach
- 👤 Harald Portig
- 👤 Thomas Campbell Wade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:07
CPC Classifications
H; H02; H02P; H02P6/00; H02P6/06; Y; Y10; Y10S; Y10S388/00; Y10S388/907; Y10S388/911
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
97 words
An apparatus for high resolution speed control of a DC motor comprising; a motor control circuit; and a phase accumulator receiving a cyclical reference clock signal, said phase accumulator comprising a phase offset circuit and a count register, said count register incrementing at each cycle of said cyclical reference clock signal, wherein an amount said count register increments is greater than one and is determined by said phase offset circuit, so that said phase accumulator sends a frequency reference to an input of said motor control circuit to provide high resolution speed control of said DC motor.
Claim 2
Independent Claim
97 words
An apparatus for high resolution speed control of a DC motor comprising; a motor control circuit; and a phase accumulator receiving a cyclical reference clock signal, said phase accumulator comprising a phase offset circuit and a count register, said count register incrementing at each cycle of said cyclical reference clock signal, wherein an amount said count register increments is greater than one and is determined by said phase offset circuit, so that said phase accumulator sends a frequency reference to an input of said motor control circuit to provide high resolution speed control of said DC motor.
Claim 3
Dependent Claim
55 words
An apparatus for high resolution speed control of a DC motor as recited in claim 1, further comprising a post divider for dividing an output of said phase accumulator by an integer of at least one, wherein an average frequency is provided to set a speed of said motor with a high degree of accuracy.
Claim 4
Dependent Claim
38 words
An apparatus for high resolution speed control of a DC motor as recited in claim 1, wherein said count register of said phase accumulator has a count which is incremented on each clock cycle by a variable amount.
Claim 5
Dependent Claim
77 words
An apparatus for high resolution speed control of a DC motor as recited in claim 3, wherein said phase accumulator never reloads, so that once a maximum count value is exceeded, bits of said count above a most-significant bit are truncated, leaving only a remainder, as defined as follows: Count t+1 =(Count t +Phase Offset)modulo 2 n , where Phase Offset=an amount to increment on each of said count, and n=a number of bits comprising said count.
Claim 6
Dependent Claim
28 words
An apparatus for high resolution speed control of a DC motor as recited in claim 4, wherein on a following cycle, said count continues incrementing from said remainder.
Claim 7
Dependent Claim
35 words
An apparatus for high resolution speed control of a DC motor as recited in claim 5, wherein said count is utilized to generate a binary output by tapping off said most-significant bit of said count.
Claim 8
Dependent Claim
69 words
An apparatus for high resolution speed control of a DC motor as recited in claim 6, wherein an output waveform obtained from said most-significant bit of said count is an irregular waveform, which over a long period, produces an average output frequency of: F.sub.MSB avg =(F.sub.CLK *Phase Offset)/2.sup.n, where F MSB avg =an average output waveform frequency over 2 n clock cycles, and F CLK =an input clock frequency.
Claim 9
Dependent Claim
70 words
An apparatus for high resolution speed control of a DC motor as recited in claim 7, wherein an entire cycle repeats at least every 2 n clock cycles, and wherein resolution of an output frequency is determined by a change in frequency produced by a change in an output of said phase offset circuit equal to one, producing a resulting absolute resolution in Hertz of F clk /2 n .
Claim 10
Dependent Claim
24 words
An apparatus for high resolution speed control of a DC motor as recited in claim 1, wherein said motor control circuit comprises a phase-locked-loop.
Claim 11
Independent Claim
106 words
An apparatus for high resolution speed control of a DC motor system comprising: a DC motor assembly controlled by a reference frequency generation circuit, said reference frequency generation circuit comprising: a crystal oscillator providing a cyclical reference signal, and a phase accumulator having a phase offset circuit and a count register, said count register incrementing for each cycle of said cyclical reference signal, wherein an amount said count register increments is greater than one and is determined by said phase offset circuit, so that said phase accumulator sends a reference frequency to an input of said DC motor assembly, said crystal oscillator driving said phase accumulator.
Claim 12
Independent Claim
106 words
An apparatus for high resolution speed control of a DC motor system comprising: a DC motor assembly controlled by a reference frequency generation circuit, said reference frequency generation circuit comprising: a crystal oscillator providing a cyclical reference signal, and a phase accumulator having a phase offset circuit and a count register, said count register incrementing for each cycle of said cyclical reference signal, wherein an amount said count register increments is greater than one and is determined by said phase offset circuit, so that said phase accumulator sends a reference frequency to an input of said DC motor assembly, said crystal oscillator driving said phase accumulator.
Claim 13
Dependent Claim
38 words
An apparatus for high resolution speed control of a DC motor as recited in claim 10, further comprising a selectable post divide circuit for dividing an output of said phase accumulator by an integer of at least one.
Claim 14
Dependent Claim
27 words
An apparatus for high resolution speed control of a DC motor as recited in claim 10, wherein said DC motor assembly is an integrated DC motor assembly.
Claim 15
Dependent Claim
36 words
An apparatus for high resolution speed control of a DC motor as recited in claim 11, wherein said post divide circuit is based upon at least a most-significant bit of an output of said phase accumulator.
Claim 16
Dependent Claim
29 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 10, further comprising a phase-locked loop to govern velocity of said DC motor.
Claim 17
Dependent Claim
30 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 10, further comprising a speed discriminator system to govern velocity of said DC motor.
Claim 18
Dependent Claim
46 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 10, further comprising a post divide circuit for dividing an output of said accumulator by an integer of at least one to preserve overall speed accuracy over a wide range.
Claim 19
Dependent Claim
82 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 16, wherein a resulting reference clock which is sent to said DC motor has an average output frequency of: F.sub.REFCLK Avg =(F.sub.CLK *Phase Offset)/2.sup.n *Post Divide, where F REFCLK Avg =an average frequency reference sent to said DC motor, F CLK =an input clock frequency, Phase Offset=an amount to increment on each count, and n=a number of bits in said count, and Post Divide=an integer number.
Claim 20
Dependent Claim
81 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 17, wherein a motor shaft frequency is determined by the following formula: F.sub.MOTOR =(F.sub.CLK *Phase Offset)/(2.sup.n *Post Divide*Motor IC Frequency Divide*Motor Feedback Ratio), where Motor IC Frequency Divide=a divide ratio set inside a driver IC of said DC motor, Motor Feedback Ratio=a ratio between cycles of one of an encoder, a Hall-effect, and a frequency generated feedback waveform per complete cycle of said motor shaft.
Claim 21
Dependent Claim
31 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 10, wherein said phase accumulator has a relative resolution inversely proportional to an output frequency.
Claim 22
Dependent Claim
40 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 10, further comprising a programmable binary divider disposed between said phase accumulator and said DC motor assembly to minimize degradation in said relative resolution.
Claim 23
Dependent Claim
54 words
An apparatus for high resolution speed control of a DC motor system as recited in claim 20, wherein a maximum timing error of said output signal is limited to plus or minus one half of one period of said phase accumulator input clock, when compared to an ideal clock with an equal average phase.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |