Multichannel viterbi decoder

Claim 2

A communication station for communicating multichannel data communications including simultaneously receiving and processing multiple channels of data at independent rates which share the same selected bandwidth comprising: a demodulator means for receiving a multichannel data communication signal having multiple data channels at independent data rates on said selected bandwidth; despreading means for separating selected channels of data of the received signal and identifying the data rate for each channel; a plurality of decoding means; each said decoding means decoding a separated channel of the multichannel data communication at an assigned data rate; said plurality of decoding means sharing a common decoding memory; and control means for directing each separated channel to one of said decoding means and assigning that decoding means a data rate responsive to the identification of data rates by said despreading means.

Claim 3

The communication station of claim 1 wherein said common decoder memory includes a state metric memory and a traceback memory which are used for processing all of the separated channels being decoded during said decoding.

Claim 4

The communication station of claim 2 wherein said state metric memory is arranged in a ping-pong system such that either a ping or a pong of said ping-pong system can be written to or read from at the same time.

Claim 5

The communication station of claim 1 further comprising a Euclidean distance calculation engine as a shared resource for said plurality of decoding means; said Euclidean distance calculation engine for computing the distances from a received symbol of a channel being decoded to each of four QPSK constellation points and for identifying the closest of said four QPSK constellation points for each said received symbol.

Claim 6

The communication station of claim 4 wherein said. Euclidean distance calculation engine is associated with said control means and operates with respect to all symbols of the channels which are directed to said decoding means.

Claim 7

The communication station of claim 1 wherein: the independent data rates include a maximum data rate, and independent data rates less than said maximum data rate include proportional duplicated data.

Claim 8

The communication station of claim 6 further comprising a decoder interface as a shared resource for said plurality of decoding means and said decoder interface adds said proportional duplicated data for independent data rates less than said maximum rate coherently using saturating logic.

Claim 9

The communication station of claim 1 wherein each said decoding means include an add-compare-select circuit where each of said add-compare-select circuits process each separated channel with a Viterbi algorithm using saturating logic to arrive at a best metric for use in traceback processing of symbols of channel data being decoded and each said best metric is post-normalized.

Claim 10

A low-power, high-speed multichannel Viterbi decoder for simultaneously decoding multiple data channels at independent data rates for use in a spread spectrum modulation receiver comprising: a decoder interface for receiving at least four data channels, at independent data rates, and for determining the data rate of each channel, each data channel comprising a plurality of symbols wherein a despread data channel having a data rate less than a maximum data rate includes proportional duplicated symbols; a Euclidean distance calculation engine for receiving said symbols from said at least four data channels, for computing distances between each said received symbol being decoded and each of four QPSK constellation points, and for outputting the closest of said four QPSK constellation points for each said received symbol; at least four add-compare-select (ACS) circuits, coupled to said calculation engine, for processing said constellation points of said at least four data channels at an assigned data rate; a state metric memory and a traceback memory, coupled to said ACS circuits, for processing said at least four data channels being decoded; an ACS processor, coupled to said ACS circuits,. for coordinating the processing of said ACS circuits; a traceback processor, coupled to said ACS circuits, for arriving at a decoded symbol for all data channels; and a receiver system interface for coupling the multichannel Viterbi decoder with additional processors.

Claim 11

A low-power, high-speed multichannel Viterbi decoder for simultaneously decoding multiple data channels at independent data rates for use in a spread spectrum modulation receiver comprising: a decoder interface for receiving at least four data channels, at independent data rates, and for determining the data rate of each channel, each data channel comprising a plurality of symbols wherein a despread data channel having a data rate less than a maximum data rate includes proportional duplicated symbols; a Euclidean distance calculation engine for receiving said symbols from said at least four data channels, for computing distances between each said received symbol being decoded and each of four QPSK constellation points, and for outputting the closest of said four QPSK constellation points for each said received symbol; at least four add-compare-select (ACS) circuits, coupled to said calculation engine, for processing said constellation points of said at least four data channels at an assigned data rate; a state metric memory and a traceback memory, coupled to said ACS circuits, for processing said at least four data channels being decoded; an ACS processor, coupled to said ACS circuits,. for coordinating the processing of said ACS circuits; a traceback processor, coupled to said ACS circuits, for arriving at a decoded symbol for all data channels; and a receiver system interface for coupling the multichannel Viterbi decoder with additional processors.

Claim 12

The Viterbi decoder according to claim 9 wherein said state metric memory is arranged in a ping-pong system such that either a ping or a pong of said ping-pong system can be written to or read from at the same time.

Claim 13

The Viterbi decoder according to claim 9 wherein said decoder interface is a shared resource for at least 4 data channels and said decoder interface adds said lower data rate duplicated data coherently using saturating logic.

Claim 14

The Viterbi decoder of claim 9 wherein said ACS circuits process each separate data channel with a Viterbi algorithm using saturating logic to arrive at a best metric for use in traceback processing of symbols of channel data being decoded and each said best metric is post-normalized.