Apparatus and method for correcting errors in a communication system

Claim 3

The system of claim 1, wherein said tie breaker counts the flags to generate a pass signal each time the score higher than said preset threshold level is generated, if the number of said flags reaches a predetermined value.

Claim 4

The system of claim 2, wherein said pass signal is supplied to said RS decoder for indicating an uncorrectable codeword.

Claim 5

The system of claim 2, wherein said predetermined value corresponds to erasure-correcting capability of said RS decoder.

Claim 6

The system of claim 1, wherein said decoding control circuit supplies said RS decoder with a word composed of all 0 bits when said flag is generated, and supplies said RS decoder with said decoded word when no flag is generated.

Claim 7

The system of claim 1, further comprising a deinterleaver coupled between said Viterbi decoder and said RS decoder for processing said decoded word.

Claim 8

The system of claim 1, wherein said score is processed by said deinterleaver in synchronism with said decoded word.

Claim 9

The system of claim 1, wherein said RS decoder decodes said decoded word in an error correction mode, and decodes said erasure in an erasure correction mode.

Claim 10

In an error correction system, a method of decoding a codeword comprising the steps of: determining the number of errors detected in a word of said codeword; decoding said codeword by an RS decoder in an error correction mode if said number is not higher than a preset threshold level; and replacing said word with an erasure supplied to said RS decoder for decoding in an erasure correction mode if said number is higher than said preset threshold level.

Claim 11

In an error correction system, a method of decoding a codeword comprising the steps of: determining the number of errors detected in a word of said codeword; decoding said codeword by an RS decoder in an error correction mode if said number is not higher than a preset threshold level; and replacing said word with an erasure supplied to said RS decoder for decoding in an erasure correction mode if said number is higher than said preset threshold level.

Claim 12

The method of claim 9, further comprising decoding said codeword in accordance with the Viterbi decoding algorithm, before said step of determining the number of errors.

Claim 13

A digital satellite television system comprising: a transmitter for generating a stream of digital packets representing video and audio signals, said transmitter having first and second encoders for generating error correction data included in said packets; a satellite for receiving and retransmitting said stream of digital packets; and a receiver for receiving said stream of digital packets retransmitted by said satellite and generating said video and audio signals to be supplied to a TV set, said receiver including: first and second decoders for decoding the error correction data provided by said first and second encoders; an error detection circuit for determining the number of errors detected in a word decoded by said first decoder; and a decoding control circuit for replacing the decoded word with an erasure supplied to said second decoder if said number of errors exceeds a preset threshold level.

Claim 14

A digital satellite television system comprising: a transmitter for generating a stream of digital packets representing video and audio signals, said transmitter having first and second encoders for generating error correction data included in said packets; a satellite for receiving and retransmitting said stream of digital packets; and a receiver for receiving said stream of digital packets retransmitted by said satellite and generating said video and audio signals to be supplied to a TV set, said receiver including: first and second decoders for decoding the error correction data provided by said first and second encoders; an error detection circuit for determining the number of errors detected in a word decoded by said first decoder; and a decoding control circuit for replacing the decoded word with an erasure supplied to said second decoder if said number of errors exceeds a preset threshold level.

Claim 15

The system of claim 11, wherein said second decoder comprises an RS decoder for decoding RS data received from said transmitter.

Claim 16

The system of claim 12, wherein said first decoder comprises a Viterbi decoder for decoding a convolutional code received from said transmitter.

Claim 17

The system of claim 13, wherein said RS decoder further decodes the word decoded by said Viterbi decoder if said number of errors does not exceed the preset threshold level.

Claim 18

The system of claim 14, wherein said receiver further comprises a tie breaker for generating decoding control signals.

Claim 19

The system of claim 15, wherein said tie breaker counts the number of the decoded words having the number of errors higher than said preset threshold level to generate a pass signal supplied to said RS decoder each time the number of errors higher than said preset threshold level is detected, if said number of the decoded words exceeds a predetermined value.

Claim 20

The system of claim 16, wherein said tie breaker prevents said decoding control circuit from replacing the decoded word with an erasure, if said number of the decoded words having the number of errors higher than said preset threshold level exceeds said predetermined value.

Claim 21

The system of claim 17, wherein said predetermined value corresponds to erasure-correcting capability of said RS decoder.

Claim 22

The system of claim 18, wherein said decoding control circuit comprises a multiplexer for supplying said RS decoder with a word composed of all 0 bits when the number of errors higher than said preset threshold level is detected, if said number of the decoded words does not exceed said predetermined value.

Claim 23

The system of claim 19, wherein said multiplexer supplies said RS decoder with said decoded word when the detected number of errors does not exceed said preset threshold level.