US5995349A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protection device for solid state switched power electronics
Assignee: Fairchild Semiconductor Corp
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Filing: 1997-10-06
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Granted: 1999-11-30
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Expires: 2017-10-06
Abstract
Abstract A circuit and method of protecting the antiparallel diodes of a power bridge circuit from stress induced failures caused by the fast operation of the power switches. An auxiliary power switch is provided in parallel to the main power switch which is operable during the reverse recovery of the antiparallel diode, after which the main power switch carries the bulk of the switch current.
Inventors
- 👤 Victor A. K. Temple
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:44
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0814
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
51 words
In a bridge circuit having two series connected, fast operating power switches each with an antiparallel diode, the improvement comprising means for providing a current path in parallel with the fast operating power switch during the reverse recovery of the antiparallel diode, said parallel current path including a slower operating switch.
Claim 2
Dependent Claim
51 words
In a bridge circuit having two series connected, fast operating power switches each with an antiparallel diode, the improvement comprising means for providing a current path in parallel with the fast operating power switch during the reverse recovery of the antiparallel diode, said parallel current path including a slower operating switch.
Claim 3
Dependent Claim
115 words
A semiconductor module including a half-bridge circuit comprising: a half-bridge circuit having two portions; each portion including in parallel: (i) a main MOS-controlled thyristor as a main switch, (ii) a diode, and (iii) a diode protection circuit for reducing stress on the diode in the other portion of the half-bridge circuit; the diode protection circuit including in series: (i) an auxiliary MOS-controlled thyristor with a substantially lower forward voltage drop than the main MOS-controlled thyristor, and (ii) a saturable inductor; and each portion including means for delaying the turn-on of the main MOS-controlled thyristor relative to the auxiliary MOS-controlled thyristor and for simultaneously turning off both the main MOS-controlled thyristor and the auxiliary MOS-controlled thyristor.
Claim 4
Dependent Claim
115 words
A semiconductor module including a half-bridge circuit comprising: a half-bridge circuit having two portions; each portion including in parallel: (i) a main MOS-controlled thyristor as a main switch, (ii) a diode, and (iii) a diode protection circuit for reducing stress on the diode in the other portion of the half-bridge circuit; the diode protection circuit including in series: (i) an auxiliary MOS-controlled thyristor with a substantially lower forward voltage drop than the main MOS-controlled thyristor, and (ii) a saturable inductor; and each portion including means for delaying the turn-on of the main MOS-controlled thyristor relative to the auxiliary MOS-controlled thyristor and for simultaneously turning off both the main MOS-controlled thyristor and the auxiliary MOS-controlled thyristor.
Claim 5
Dependent Claim
88 words
In a half-bridge circuit having in series two alternately activated main MOS-controlled thyristors, each main MOS-controlled thyristor being in parallel with: (i) a diode, and (ii) an auxiliary MOS-controlled thyristor in series with an inductor, the method of operating the half-bridge circuit to reduce diode failure comprising the steps of: (a) delaying activation of a main MOS-controlled thyristor relative to activating an auxiliary MOS-controlled thyristor in parallel with the main MOS-controlled thyristor; and (b) simultaneously deactivating both the main MOS-controlled thyristor and the in parallel auxiliary MOS-controlled thyristor.
Claim 6
Dependent Claim
88 words
In a half-bridge circuit having in series two alternately activated main MOS-controlled thyristors, each main MOS-controlled thyristor being in parallel with: (i) a diode, and (ii) an auxiliary MOS-controlled thyristor in series with an inductor, the method of operating the half-bridge circuit to reduce diode failure comprising the steps of: (a) delaying activation of a main MOS-controlled thyristor relative to activating an auxiliary MOS-controlled thyristor in parallel with the main MOS-controlled thyristor; and (b) simultaneously deactivating both the main MOS-controlled thyristor and the in parallel auxiliary MOS-controlled thyristor.
Claim 7
Dependent Claim
87 words
In a half-bridge circuit having two series connected MOS-controlled thyristors, each MOS-controlled thyristor hating a diode in parallel therewith each MOS-controlled thyristor, a protective device for reducing stress of the diode comprising: alternate path means for providing an alternative path for the current through the half-bridge circuit during reverse recovery of said diodes; and control means for delaying the turn-on of a MOS-controlled thyristor relative to the turn-on of the alternate path means and for simultaneously turning off both the MOS-controlled thyristor and the alternate path means.
Claim 8
Dependent Claim
87 words
In a half-bridge circuit having two series connected MOS-controlled thyristors, each MOS-controlled thyristor hating a diode in parallel therewith each MOS-controlled thyristor, a protective device for reducing stress of the diode comprising: alternate path means for providing an alternative path for the current through the half-bridge circuit during reverse recovery of said diodes; and control means for delaying the turn-on of a MOS-controlled thyristor relative to the turn-on of the alternate path means and for simultaneously turning off both the MOS-controlled thyristor and the alternate path means.
References Cited (Backward Citations)
US5307005A
Cited
US5463344A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |