Semiconductor chip package and fabrication method thereof

Claim 2

A semiconductor chip package, comprising; a semiconductor chip having a plurality of chip pads formed thereon; a passivation film formed on said semiconductor chip with the chip pads exposed; a plurality of metal wirings directly coupled to the chip pads formed on the passivation film; external balls directly electrically connected to each of the metal wirings; and a molding resin layer formed on a first surface of the semiconductor chip such that upper portions of the external balls protrude from said molding resin layer.

Claim 3

The package of claim 1, wherein said plurality of metal wiring comprises one of copper (Cu) and gold (Au).

Claim 4

The package of claim 1, wherein the external balls are made of solder.

Claim 5

The package of claim 1, further comprises an external protection plate to enclose the sides and a second surface of the semiconductor chip and a resin to seal the gap between the semiconductor chip and the external protection plate.

Claim 6

A semiconductor chip package, comprising: a semiconductor chip having a plurality of chip pads formed thereon; a passivation film formed on said semiconductor chip such that said plurality of chip pads of the semiconductor chip are exposed; a plurality of metal wiring layers attached to the passivation film with an adherent; a connecting metal for conductively coupling each metal wiring layer and each chip pad; a plurality of external balls attached to each metal wiring layer; and a molding resin layer formed on a first surface of the semiconductor chip such that an outer end of each external ball protrudes from said molding resin.

Claim 7

A semiconductor chip package, comprising: a semiconductor chip having a plurality of chip pads formed thereon; a passivation film formed on said semiconductor chip such that said plurality of chip pads of the semiconductor chip are exposed; a plurality of metal wiring layers attached to the passivation film with an adherent; a connecting metal for conductively coupling each metal wiring layer and each chip pad; a plurality of external balls attached to each metal wiring layer; and a molding resin layer formed on a first surface of the semiconductor chip such that an outer end of each external ball protrudes from said molding resin.

Claim 8

The package of claim 5, wherein said metal wiring layer comprises one of copper (Cu) or gold (Au).

Claim 9

The package of claim 5, wherein the external ball is made of solder.

Claim 10

The package of claim 5, further comprising an external protection plate to enclose sides and a second surface of the semiconductor chip and a resin to seal the gap between the semiconductor chip and the external protection plate.

Claim 11

A chip package, comprising: an integrated chip having a plurality of chip pads on a first surface; a passivation film formed on the first surface of said integrated chip with said plurality of chip pads exposed; a plurality of conductive wires formed on the passivation film such that a corresponding conductive wire is conductively coupled to a corresponding chip pad; a plurality of conductive media formed of a single piece, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wire; and a molding layer formed on said plurality of conductive wires, said molding layer having a prescribed thickness which is less than the prescribed height such that portions of said plurality of conductive media protrude from said molding layer.

Claim 12

A chip package, comprising: an integrated chip having a plurality of chip pads on a first surface; a passivation film formed on the first surface of said integrated chip with said plurality of chip pads exposed; a plurality of conductive wires formed on the passivation film such that a corresponding conductive wire is conductively coupled to a corresponding chip pad; a plurality of conductive media formed of a single piece, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wire; and a molding layer formed on said plurality of conductive wires, said molding layer having a prescribed thickness which is less than the prescribed height such that portions of said plurality of conductive media protrude from said molding layer.

Claim 13

The chip package of claim 9, wherein said molding layer is directly formed on said plurality of conductive wires.

Claim 14

The chip package of claim 9, wherein said integrated chip is a semiconductor chip.

Claim 15

The chip package of claim 9, wherein each of said plurality of conductive wires is directly connected to each of said plurality of chip pads.

Claim 16

The chip package of claim 9, wherein each of said plurality of conductive wires is conductively coupled to each of said plurality of chip pads by a conductive connecting member.

Claim 17

The chip package of claim 13, wherein said plurality of conductive wires is made of a metallic material.

Claim 18

The chip package of claim 14, wherein the metallic material is one of copper and gold.

Claim 19

The chip package of claim 9, wherein said plurality of conductive wires is attached to the passivation film by an adherent.

Claim 20

The chip package of claim 9, wherein said molding layer is made of resin.

Claim 21

The chip package of claim 9, wherein each of said plurality of conductive media is a solder ball.

Claim 22

The chip package of claim 9, wherein said portions protruding above the molding layer has a circular shape.

Claim 23

The chip package of claim 19, wherein said plurality of conductive media is made of solder.

Claim 24

The chip package of claim 9, wherein the thickness of the molding layer is about half the height of the conductive media.

Claim 25

The chip package of claim 9, further comprising a protection member bonded to a second surface of said integrated chip, the first and second surfaces being opposing surfaces.

Claim 26

The chip package of claim 22, wherein said protection member includes a recess such that the sides of said integrated chip are enclosed.

Claim 27

The chip package of claim 23 further comprising a resin filling any gaps between said integrated chip and said protection member.

Claim 28

A chip package, comprising: an integrated chip having a plurality of chip pads on a first surface; a passivation film formed on the first surface of the integrated chip such that said plurality of chip pads are exposed; a plurality of conductive wires, wherein a corresponding one of said plurality of conductive wires is coupled to a corresponding chip pad; a plurality of conductive media, each having a first prescribed height, wherein a corresponding one of said plurality of conductive media is coupled to a corresponding one of said plurality of conductive wires; a molding layer formed on the first surface of said integrated chip such that portions of said plurality of conductive media protrude from said molding layer; and a protection member bonded to a second surface of said integrated chip, the first and second surfaces being opposing surfaces.

Claim 29

A chip package, comprising: an integrated chip having a plurality of chip pads on a first surface; a passivation film formed on the first surface of the integrated chip such that said plurality of chip pads are exposed; a plurality of conductive wires, wherein a corresponding one of said plurality of conductive wires is coupled to a corresponding chip pad; a plurality of conductive media, each having a first prescribed height, wherein a corresponding one of said plurality of conductive media is coupled to a corresponding one of said plurality of conductive wires; a molding layer formed on the first surface of said integrated chip such that portions of said plurality of conductive media protrude from said molding layer; and a protection member bonded to a second surface of said integrated chip, the first and second surfaces being opposing surfaces.

Claim 30

The chip package of claim 25, wherein said protection member includes a recess to enclose the sides of said integrated chip.

Claim 31

The chip package of claim 26, further comprising a resin filling any gaps between said integrated chip and said protection member.

Claim 32

The chip package of claim 25, wherein said molding layer is directly formed on the conductive wiring.

Claim 33

The chip package of claim 25, wherein said integrated chip is a semiconductor chip.

Claim 34

The chip package of claim 25, wherein said plurality of conductive wires comprise metal wires being one of copper (Cu) and gold (Au).

Claim 35

The chip package of claim 25, wherein each of said plurality of conductive media comprises a solder ball.

Claim 36

The chip package of claim 25, wherein said plurality of conductive wires is attached to the passivation film by an adherent.

Claim 37

The chip package of claim 25, wherein said molding layer is made of resin.