Method of making SRAM having part of load resistance layer functions as power supply line

Claim 1

A method of manufacturing a static memory device whose memory cell is composed of transfer MOS transistors and a flip-flop which is composed of drive MOS transistors and load resistors, gates of said transfer MOS transistors being connected to a word line and said load resistors being connected to a power supply line, comprising the steps of: forming a first insulating layer on a semiconductor substrate in a memory cell region; forming a first conductive layer on said first insulating layer in said memory cell region; performing a first patterning process to said first conductive layer; forming a second insulating layer in said memory cell region; forming a second conductive layer with regions for said load resistors in said memory cell region; performing a second patterning process to a lamination film composed of said first insulating layer, said first conductive layer, said second insulating layer and said second conductive layer, wherein a lamination section of said first insulating layer and said first conductive layer are separated through said first and second patterning processes into first to fourth portions, said first and second portions respectively functioning as parts of said word line which are connected to each other and as said gates of said transfer MOS transistors, and said third and fourth portions respectively functioning as gates of said drive MOS transistors, and wherein said second conductive layer is separated through said second patterning process into fifth and sixth portions, said fifth and sixth portions respectively functioning as parts of said power supply line which are connected to each other and as said load resistors connected to said parts of said power supply line, and wherein said fifth and sixth portions are laminated on a set of said first and third portions and a set of said second and fourth portions via said second insulating layer, respectively; and connecting said fifth and sixth portions to said third and fourth portions through contacts such that said gates of said drive MOS transistors are connected to said parts of said power supply line via said load resistors, respectively.

Claim 2

A method of manufacturing a static memory device whose memory cell is composed of transfer MOS transistors and a flip-flop which is composed of drive MOS transistors and load resistors, gates of said transfer MOS transistors being connected to a word line and said load resistors being connected to a power supply line, comprising the steps of: forming a first insulating layer on a semiconductor substrate in a memory cell region; forming a first conductive layer on said first insulating layer in said memory cell region; performing a first patterning process to said first conductive layer; forming a second insulating layer in said memory cell region; forming a second conductive layer with regions for said load resistors in said memory cell region; performing a second patterning process to a lamination film composed of said first insulating layer, said first conductive layer, said second insulating layer and said second conductive layer, wherein a lamination section of said first insulating layer and said first conductive layer are separated through said first and second patterning processes into first to fourth portions, said first and second portions respectively functioning as parts of said word line which are connected to each other and as said gates of said transfer MOS transistors, and said third and fourth portions respectively functioning as gates of said drive MOS transistors, and wherein said second conductive layer is separated through said second patterning process into fifth and sixth portions, said fifth and sixth portions respectively functioning as parts of said power supply line which are connected to each other and as said load resistors connected to said parts of said power supply line, and wherein said fifth and sixth portions are laminated on a set of said first and third portions and a set of said second and fourth portions via said second insulating layer, respectively; and connecting said fifth and sixth portions to said third and fourth portions through contacts such that said gates of said drive MOS transistors are connected to said parts of said power supply line via said load resistors, respectively.

Claim 8

A method of manufacturing a static memory device whose memory cell is composed of transfer MOS transistors and a flip-flop which is composed of drive MOS transistors and load resistors, gates of said transfer MOS transistors being connected to a word line and said load resistors being connected to a power supply line, comprising the steps of: forming first to fourth gate structure patterns respectively corresponding first to fourth MOS transistors on a semiconductor substrate, wherein each of said first to fourth gate structure patterns is composed of a gate insulating layer pattern and a conductive layer pattern on said gate insulating layer pattern, and said third and fourth gate structure patterns function as parts of said word line which are connected together; forming a first conductive layer pattern on said first and third gate structure patterns via a first insulating layer pattern and a second conductive layer pattern on said second and fourth gate structure patterns via a second insulating layer pattern, wherein portions of said first and second conductive layer patterns above said third and fourth gate structure patterns function parts of said power supply line which are connected together, and wherein portions of said first and second conductive layer patterns above said first and second gate structure includes regions having resistance values higher than other portion, the regions functioning as load resistors; and connecting said first and second gate structure patterns to said first and second conductive layer pattern, respectively.

Claim 9

A method of manufacturing a static memory device whose memory cell is composed of transfer MOS transistors and a flip-flop which is composed of drive MOS transistors and load resistors, gates of said transfer MOS transistors being connected to a word line and said load resistors being connected to a power supply line, comprising the steps of: forming first to fourth gate structure patterns respectively corresponding first to fourth MOS transistors on a semiconductor substrate, wherein each of said first to fourth gate structure patterns is composed of a gate insulating layer pattern and a conductive layer pattern on said gate insulating layer pattern, and said third and fourth gate structure patterns function as parts of said word line which are connected together; forming a first conductive layer pattern on said first and third gate structure patterns via a first insulating layer pattern and a second conductive layer pattern on said second and fourth gate structure patterns via a second insulating layer pattern, wherein portions of said first and second conductive layer patterns above said third and fourth gate structure patterns function parts of said power supply line which are connected together, and wherein portions of said first and second conductive layer patterns above said first and second gate structure includes regions having resistance values higher than other portion, the regions functioning as load resistors; and connecting said first and second gate structure patterns to said first and second conductive layer pattern, respectively.